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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id n12sm2993534otl.22.2019.02.28.08.29.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Feb 2019 08:29:07 -0800 (PST) Date: Thu, 28 Feb 2019 10:29:06 -0600 From: Rob Herring To: Neil Armstrong Subject: Re: [PATCH 4/8] dt-bindings: usb: dwc3: Add Amlogic G12A DWC3 Glue Bindings Message-ID: <20190228162906.GA2387@bogus> References: <20190212151413.24632-1-narmstrong@baylibre.com> <20190212151413.24632-5-narmstrong@baylibre.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190212151413.24632-5-narmstrong@baylibre.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190228_082909_475947_9B906183 X-CRM114-Status: GOOD ( 24.89 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, balbi@kernel.org, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, kishon@ti.com, hminas@synopsys.com, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Tue, Feb 12, 2019 at 04:14:09PM +0100, Neil Armstrong wrote: > Adds the bindings for the Amlogic G12A USB Glue HW. > > The Amlogic G12A SoC Family embeds 2 USB Controllers : > - a DWC3 IP configured as Host for USB2 and USB3 > - a DWC2 IP configured as Peripheral USB2 Only > > A glue connects these both controllers to 2 USB2 PHYs, > and optionnally to an USB3+PCIE Combo PHY shared with the PCIE controller. > > The Glue configures the UTMI 8bit interfaces for the USB2 PHYs, including > routing of the OTG PHY between the DWC3 and DWC2 controllers, and > setups the on-chip OTG mode selection for this PHY. > > The PHYs are children of the Glue node since the Glue controls the interface > with the PHY, not the DWC3 controller. > > The PHY interconnect is handled into ports subnodes, which eases describing > which PHY is enabled (like the USB3 shared PHY) and futures layouts on > derivatives of the G12A Family. > > Signed-off-by: Neil Armstrong > --- > .../devicetree/bindings/usb/amlogic,dwc3.txt | 109 ++++++++++++++++++ > 1 file changed, 109 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt > index 9a8b631904fd..c7c4726ef10d 100644 > --- a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt > +++ b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt > @@ -40,3 +40,112 @@ Example device nodes: > phy-names = "usb2-phy", "usb3-phy"; > }; > }; > + > +Amlogic Meson G12A DWC3 USB SoC Controller Glue > + > +The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3 > +in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode > +only. > + > +A glue connects the DWC3 core to USB2 PHYs and optionnaly to an USB3 PHY. > + > +One of the USB2 PHY can be re-routed in peripheral mode to a DWC2 USB IP. > + > +The DWC3 Glue controls the PHY routing and power, an interrupt line is > +connected to the Glue to serve as OTG ID change detection. > + > +Required properties: > +- compatible: Should be "amlogic,meson-g12a-usb-ctrl" > +- clocks: a handle for the "USB" clock > +- clock-names: must be "usb" > +- resets: a handle for the shared "USB" reset line > +- reset-names: must be "usb" -name for a single entry is pointless. > +- reg: The base address and length of the registers > +- interrupts: the interrupt specifier for the OTG detection > + > +Required child nodes: > + > +USB Ports are described as child 'port' nodes grouped under a 'ports' node, > +with #address-cells, #size-cells specified. > + > +Each 'port' sub-node identifies a possible USB Port served by an USB PHY > +identified by the 'phy' property as decribed in ../phy/phy-bindings.txt > + > +Each 'port' is identified by a reg property to number the port. > + > +The following table lists for each supported model the port number > +corresponding to each PHY serving a physical USB Port. > + > + Family Port 0 Port 1 Port 2 Port 3 Port 4 > +--------------------------------------------------------------- > + G12A USBHOST_A USBOTG_B Reserved Reserved USB3_0 > + > +A child node must exist to represent the core DWC3 IP block. The name of > +the node is not important. The content of the node is defined in dwc3.txt. > + > +A child node must exist to represent the core DWC2 IP block. The name of > +the node is not important. The content of the node is defined in dwc2.txt. > + > +PHY documentation is provided in the following places: > +- Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt > +- Documentation/devicetree/bindings/phy/meson-g12a-usb3-pcie-phy.txt > + > + > +Example device nodes: > + usb: usb@ffe09000 { > + compatible = "amlogic,meson-g12a-usb-ctrl"; > + reg = <0x0 0xffe09000 0x0 0xa0>; > + interrupts = ; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&clkc CLKID_USB>; > + clock-names = "usb"; > + resets = <&reset RESET_USB>; > + reset-names = "usb"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* USB2 Port 0 */ > + usb20: port@0 { > + reg = <0>; > + phys = <&usb2_phy0>; 'ports' and 'port' are reserved for the graph binding. Don't use it for your own thing. Can't you just make 'phys' a list using 0 phandle if you need to skip entries. > + }; > + > + /* USB2 Port 1 */ > + usb21: port@1 { > + reg = <1>; > + phys = <&usb2_phy1>; > + }; > + > + /* USB3 Port 0 */ > + usb3: port@4 { > + reg = <4>; > + phys = <&usb3_pcie_phy PHY_TYPE_USB3>; > + }; > + }; > + > + dwc2: usb@ff400000 { > + compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; > + reg = <0x0 0xff400000 0x0 0x40000>; > + interrupts = ; > + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; > + clock-names = "ddr"; > + dr_mode = "peripheral"; > + g-rx-fifo-size = <192>; > + g-np-tx-fifo-size = <128>; > + g-tx-fifo-size = <128 128 16 16 16>; > + }; > + > + dwc3: dwc3@ff500000 { usb@... or usb3@... > + compatible = "snps,dwc3"; > + reg = <0x0 0xff500000 0x0 0x100000>; > + interrupts = ; > + dr_mode = "host"; > + snps,dis_u2_susphy_quirk; > + snps,quirk-frame-length-adjustment; > + }; > + }; > -- > 2.20.1 > _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [4/8] dt-bindings: usb: dwc3: Add Amlogic G12A DWC3 Glue Bindings From: Rob Herring Message-Id: <20190228162906.GA2387@bogus> Date: Thu, 28 Feb 2019 10:29:06 -0600 To: Neil Armstrong Cc: gregkh@linuxfoundation.org, hminas@synopsys.com, balbi@kernel.org, kishon@ti.com, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-ID: T24gVHVlLCBGZWIgMTIsIDIwMTkgYXQgMDQ6MTQ6MDlQTSArMDEwMCwgTmVpbCBBcm1zdHJvbmcg d3JvdGU6Cj4gQWRkcyB0aGUgYmluZGluZ3MgZm9yIHRoZSBBbWxvZ2ljIEcxMkEgVVNCIEdsdWUg SFcuCj4gCj4gVGhlIEFtbG9naWMgRzEyQSBTb0MgRmFtaWx5IGVtYmVkcyAyIFVTQiBDb250cm9s bGVycyA6Cj4gLSBhIERXQzMgSVAgY29uZmlndXJlZCBhcyBIb3N0IGZvciBVU0IyIGFuZCBVU0Iz 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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id n12sm2993534otl.22.2019.02.28.08.29.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Feb 2019 08:29:07 -0800 (PST) Date: Thu, 28 Feb 2019 10:29:06 -0600 From: Rob Herring To: Neil Armstrong Subject: Re: [PATCH 4/8] dt-bindings: usb: dwc3: Add Amlogic G12A DWC3 Glue Bindings Message-ID: <20190228162906.GA2387@bogus> References: <20190212151413.24632-1-narmstrong@baylibre.com> <20190212151413.24632-5-narmstrong@baylibre.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190212151413.24632-5-narmstrong@baylibre.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190228_082909_475947_9B906183 X-CRM114-Status: GOOD ( 24.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, balbi@kernel.org, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, kishon@ti.com, hminas@synopsys.com, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Feb 12, 2019 at 04:14:09PM +0100, Neil Armstrong wrote: > Adds the bindings for the Amlogic G12A USB Glue HW. > > The Amlogic G12A SoC Family embeds 2 USB Controllers : > - a DWC3 IP configured as Host for USB2 and USB3 > - a DWC2 IP configured as Peripheral USB2 Only > > A glue connects these both controllers to 2 USB2 PHYs, > and optionnally to an USB3+PCIE Combo PHY shared with the PCIE controller. > > The Glue configures the UTMI 8bit interfaces for the USB2 PHYs, including > routing of the OTG PHY between the DWC3 and DWC2 controllers, and > setups the on-chip OTG mode selection for this PHY. > > The PHYs are children of the Glue node since the Glue controls the interface > with the PHY, not the DWC3 controller. > > The PHY interconnect is handled into ports subnodes, which eases describing > which PHY is enabled (like the USB3 shared PHY) and futures layouts on > derivatives of the G12A Family. > > Signed-off-by: Neil Armstrong > --- > .../devicetree/bindings/usb/amlogic,dwc3.txt | 109 ++++++++++++++++++ > 1 file changed, 109 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt > index 9a8b631904fd..c7c4726ef10d 100644 > --- a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt > +++ b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt > @@ -40,3 +40,112 @@ Example device nodes: > phy-names = "usb2-phy", "usb3-phy"; > }; > }; > + > +Amlogic Meson G12A DWC3 USB SoC Controller Glue > + > +The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3 > +in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode > +only. > + > +A glue connects the DWC3 core to USB2 PHYs and optionnaly to an USB3 PHY. > + > +One of the USB2 PHY can be re-routed in peripheral mode to a DWC2 USB IP. > + > +The DWC3 Glue controls the PHY routing and power, an interrupt line is > +connected to the Glue to serve as OTG ID change detection. > + > +Required properties: > +- compatible: Should be "amlogic,meson-g12a-usb-ctrl" > +- clocks: a handle for the "USB" clock > +- clock-names: must be "usb" > +- resets: a handle for the shared "USB" reset line > +- reset-names: must be "usb" -name for a single entry is pointless. > +- reg: The base address and length of the registers > +- interrupts: the interrupt specifier for the OTG detection > + > +Required child nodes: > + > +USB Ports are described as child 'port' nodes grouped under a 'ports' node, > +with #address-cells, #size-cells specified. > + > +Each 'port' sub-node identifies a possible USB Port served by an USB PHY > +identified by the 'phy' property as decribed in ../phy/phy-bindings.txt > + > +Each 'port' is identified by a reg property to number the port. > + > +The following table lists for each supported model the port number > +corresponding to each PHY serving a physical USB Port. > + > + Family Port 0 Port 1 Port 2 Port 3 Port 4 > +--------------------------------------------------------------- > + G12A USBHOST_A USBOTG_B Reserved Reserved USB3_0 > + > +A child node must exist to represent the core DWC3 IP block. The name of > +the node is not important. The content of the node is defined in dwc3.txt. > + > +A child node must exist to represent the core DWC2 IP block. The name of > +the node is not important. The content of the node is defined in dwc2.txt. > + > +PHY documentation is provided in the following places: > +- Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt > +- Documentation/devicetree/bindings/phy/meson-g12a-usb3-pcie-phy.txt > + > + > +Example device nodes: > + usb: usb@ffe09000 { > + compatible = "amlogic,meson-g12a-usb-ctrl"; > + reg = <0x0 0xffe09000 0x0 0xa0>; > + interrupts = ; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&clkc CLKID_USB>; > + clock-names = "usb"; > + resets = <&reset RESET_USB>; > + reset-names = "usb"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* USB2 Port 0 */ > + usb20: port@0 { > + reg = <0>; > + phys = <&usb2_phy0>; 'ports' and 'port' are reserved for the graph binding. Don't use it for your own thing. Can't you just make 'phys' a list using 0 phandle if you need to skip entries. > + }; > + > + /* USB2 Port 1 */ > + usb21: port@1 { > + reg = <1>; > + phys = <&usb2_phy1>; > + }; > + > + /* USB3 Port 0 */ > + usb3: port@4 { > + reg = <4>; > + phys = <&usb3_pcie_phy PHY_TYPE_USB3>; > + }; > + }; > + > + dwc2: usb@ff400000 { > + compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; > + reg = <0x0 0xff400000 0x0 0x40000>; > + interrupts = ; > + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; > + clock-names = "ddr"; > + dr_mode = "peripheral"; > + g-rx-fifo-size = <192>; > + g-np-tx-fifo-size = <128>; > + g-tx-fifo-size = <128 128 16 16 16>; > + }; > + > + dwc3: dwc3@ff500000 { usb@... or usb3@... > + compatible = "snps,dwc3"; > + reg = <0x0 0xff500000 0x0 0x100000>; > + interrupts = ; > + dr_mode = "host"; > + snps,dis_u2_susphy_quirk; > + snps,quirk-frame-length-adjustment; > + }; > + }; > -- > 2.20.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH 4/8] dt-bindings: usb: dwc3: Add Amlogic G12A DWC3 Glue Bindings Date: Thu, 28 Feb 2019 10:29:06 -0600 Message-ID: <20190228162906.GA2387@bogus> References: <20190212151413.24632-1-narmstrong@baylibre.com> <20190212151413.24632-5-narmstrong@baylibre.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20190212151413.24632-5-narmstrong@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org To: Neil Armstrong Cc: gregkh@linuxfoundation.org, hminas@synopsys.com, balbi@kernel.org, kishon@ti.com, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org On Tue, Feb 12, 2019 at 04:14:09PM +0100, Neil Armstrong wrote: > Adds the bindings for the Amlogic G12A USB Glue HW. > > The Amlogic G12A SoC Family embeds 2 USB Controllers : > - a DWC3 IP configured as Host for USB2 and USB3 > - a DWC2 IP configured as Peripheral USB2 Only > > A glue connects these both controllers to 2 USB2 PHYs, > and optionnally to an USB3+PCIE Combo PHY shared with the PCIE controller. > > The Glue configures the UTMI 8bit interfaces for the USB2 PHYs, including > routing of the OTG PHY between the DWC3 and DWC2 controllers, and > setups the on-chip OTG mode selection for this PHY. > > The PHYs are children of the Glue node since the Glue controls the interface > with the PHY, not the DWC3 controller. > > The PHY interconnect is handled into ports subnodes, which eases describing > which PHY is enabled (like the USB3 shared PHY) and futures layouts on > derivatives of the G12A Family. > > Signed-off-by: Neil Armstrong > --- > .../devicetree/bindings/usb/amlogic,dwc3.txt | 109 ++++++++++++++++++ > 1 file changed, 109 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt > index 9a8b631904fd..c7c4726ef10d 100644 > --- a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt > +++ b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt > @@ -40,3 +40,112 @@ Example device nodes: > phy-names = "usb2-phy", "usb3-phy"; > }; > }; > + > +Amlogic Meson G12A DWC3 USB SoC Controller Glue > + > +The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3 > +in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode > +only. > + > +A glue connects the DWC3 core to USB2 PHYs and optionnaly to an USB3 PHY. > + > +One of the USB2 PHY can be re-routed in peripheral mode to a DWC2 USB IP. > + > +The DWC3 Glue controls the PHY routing and power, an interrupt line is > +connected to the Glue to serve as OTG ID change detection. > + > +Required properties: > +- compatible: Should be "amlogic,meson-g12a-usb-ctrl" > +- clocks: a handle for the "USB" clock > +- clock-names: must be "usb" > +- resets: a handle for the shared "USB" reset line > +- reset-names: must be "usb" -name for a single entry is pointless. > +- reg: The base address and length of the registers > +- interrupts: the interrupt specifier for the OTG detection > + > +Required child nodes: > + > +USB Ports are described as child 'port' nodes grouped under a 'ports' node, > +with #address-cells, #size-cells specified. > + > +Each 'port' sub-node identifies a possible USB Port served by an USB PHY > +identified by the 'phy' property as decribed in ../phy/phy-bindings.txt > + > +Each 'port' is identified by a reg property to number the port. > + > +The following table lists for each supported model the port number > +corresponding to each PHY serving a physical USB Port. > + > + Family Port 0 Port 1 Port 2 Port 3 Port 4 > +--------------------------------------------------------------- > + G12A USBHOST_A USBOTG_B Reserved Reserved USB3_0 > + > +A child node must exist to represent the core DWC3 IP block. The name of > +the node is not important. The content of the node is defined in dwc3.txt. > + > +A child node must exist to represent the core DWC2 IP block. The name of > +the node is not important. The content of the node is defined in dwc2.txt. > + > +PHY documentation is provided in the following places: > +- Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt > +- Documentation/devicetree/bindings/phy/meson-g12a-usb3-pcie-phy.txt > + > + > +Example device nodes: > + usb: usb@ffe09000 { > + compatible = "amlogic,meson-g12a-usb-ctrl"; > + reg = <0x0 0xffe09000 0x0 0xa0>; > + interrupts = ; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&clkc CLKID_USB>; > + clock-names = "usb"; > + resets = <&reset RESET_USB>; > + reset-names = "usb"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* USB2 Port 0 */ > + usb20: port@0 { > + reg = <0>; > + phys = <&usb2_phy0>; 'ports' and 'port' are reserved for the graph binding. Don't use it for your own thing. Can't you just make 'phys' a list using 0 phandle if you need to skip entries. > + }; > + > + /* USB2 Port 1 */ > + usb21: port@1 { > + reg = <1>; > + phys = <&usb2_phy1>; > + }; > + > + /* USB3 Port 0 */ > + usb3: port@4 { > + reg = <4>; > + phys = <&usb3_pcie_phy PHY_TYPE_USB3>; > + }; > + }; > + > + dwc2: usb@ff400000 { > + compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; > + reg = <0x0 0xff400000 0x0 0x40000>; > + interrupts = ; > + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; > + clock-names = "ddr"; > + dr_mode = "peripheral"; > + g-rx-fifo-size = <192>; > + g-np-tx-fifo-size = <128>; > + g-tx-fifo-size = <128 128 16 16 16>; > + }; > + > + dwc3: dwc3@ff500000 { usb@... or usb3@... > + compatible = "snps,dwc3"; > + reg = <0x0 0xff500000 0x0 0x100000>; > + interrupts = ; > + dr_mode = "host"; > + snps,dis_u2_susphy_quirk; > + snps,quirk-frame-length-adjustment; > + }; > + }; > -- > 2.20.1 >