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[209.51.188.17]) by mx.google.com with ESMTPS id s12si10031763ybq.106.2019.03.01.02.44.31 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 01 Mar 2019 02:44:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([127.0.0.1]:35334 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzfeZ-0000LN-6U for alex.bennee@linaro.org; Fri, 01 Mar 2019 05:44:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53649) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzfeO-0000Je-FH for qemu-arm@nongnu.org; Fri, 01 Mar 2019 05:44:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzfeM-0008HW-7V for qemu-arm@nongnu.org; Fri, 01 Mar 2019 05:44:20 -0500 Received: from mx1.redhat.com ([209.132.183.28]:42364) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gzfeK-0008D6-7s; Fri, 01 Mar 2019 05:44:18 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 0147DA0B97; Fri, 1 Mar 2019 10:44:09 +0000 (UTC) Received: from localhost (unknown [10.43.2.182]) by smtp.corp.redhat.com (Postfix) with ESMTP id 362071001DE9; Fri, 1 Mar 2019 10:44:06 +0000 (UTC) Date: Fri, 1 Mar 2019 11:44:03 +0100 From: Igor Mammedov To: Heyi Guo Message-ID: <20190301114403.1e8324f4@redhat.com> In-Reply-To: <1551407310-32413-1-git-send-email-guoheyi@huawei.com> References: <1551407310-32413-1-git-send-email-guoheyi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Fri, 01 Mar 2019 10:44:10 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH] hw/arm/acpi: enable SHPC native hot plug X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "Michael S. Tsirkin" , qemu-devel@nongnu.org, Shannon Zhao , Heyi Guo , qemu-arm@nongnu.org, wanghaibin.wang@huawei.com Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: aQCLkQHTvl2n On Fri, 1 Mar 2019 10:28:30 +0800 Heyi Guo wrote: > After the introduction of generic PCIe root port and PCIe-PCI bridge, > we will also have SHPC controller on ARM, so just enalbe SHPC native > hot plug. Just out of curiosity, An understand the need for SHPC on plain PCI but in case of PCIe why native PCIe hotplug isn't sufficient? > Cc: Shannon Zhao > Cc: Peter Maydell > Cc: "Michael S. Tsirkin" > Cc: Igor Mammedov > Signed-off-by: Heyi Guo > Signed-off-by: Heyi Guo > --- > hw/arm/virt-acpi-build.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index 04b62c7..7849ec5 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c > @@ -265,7 +265,12 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, > aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); > aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); > aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); > - aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL), > + > + /* > + * Allow OS control for all 5 features: > + * PCIeHotplug SHPCHotplug PME AER PCIeCapability. > + */ > + aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1F), NULL), > aml_name("CTRL"))); > > ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:53685) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzfeS-0000Mq-Tb for qemu-devel@nongnu.org; Fri, 01 Mar 2019 05:44:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzfeQ-0008K5-KB for qemu-devel@nongnu.org; Fri, 01 Mar 2019 05:44:24 -0500 Date: Fri, 1 Mar 2019 11:44:03 +0100 From: Igor Mammedov Message-ID: <20190301114403.1e8324f4@redhat.com> In-Reply-To: <1551407310-32413-1-git-send-email-guoheyi@huawei.com> References: <1551407310-32413-1-git-send-email-guoheyi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] hw/arm/acpi: enable SHPC native hot plug List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Heyi Guo Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, wanghaibin.wang@huawei.com, Shannon Zhao , Peter Maydell , "Michael S. Tsirkin" , Heyi Guo On Fri, 1 Mar 2019 10:28:30 +0800 Heyi Guo wrote: > After the introduction of generic PCIe root port and PCIe-PCI bridge, > we will also have SHPC controller on ARM, so just enalbe SHPC native > hot plug. Just out of curiosity, An understand the need for SHPC on plain PCI but in case of PCIe why native PCIe hotplug isn't sufficient? > Cc: Shannon Zhao > Cc: Peter Maydell > Cc: "Michael S. Tsirkin" > Cc: Igor Mammedov > Signed-off-by: Heyi Guo > Signed-off-by: Heyi Guo > --- > hw/arm/virt-acpi-build.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index 04b62c7..7849ec5 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c > @@ -265,7 +265,12 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, > aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); > aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); > aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); > - aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL), > + > + /* > + * Allow OS control for all 5 features: > + * PCIeHotplug SHPCHotplug PME AER PCIeCapability. > + */ > + aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1F), NULL), > aml_name("CTRL"))); > > ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));