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[173.76.246.42]) by smtp.gmail.com with ESMTPSA id d51sm2988032qta.31.2019.03.03.15.38.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Mar 2019 15:38:41 -0800 (PST) Date: Sun, 3 Mar 2019 18:38:39 -0500 From: "Michael S. Tsirkin" To: Heyi Guo Message-ID: <20190303183805-mutt-send-email-mst@kernel.org> References: <1551407310-32413-1-git-send-email-guoheyi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1551407310-32413-1-git-send-email-guoheyi@huawei.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.160.193 Subject: Re: [Qemu-arm] [PATCH] hw/arm/acpi: enable SHPC native hot plug X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-devel@nongnu.org, Shannon Zhao , Heyi Guo , qemu-arm@nongnu.org, Igor Mammedov , wanghaibin.wang@huawei.com Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: Eps+GJa6/V91 On Fri, Mar 01, 2019 at 10:28:30AM +0800, Heyi Guo wrote: > After the introduction of generic PCIe root port and PCIe-PCI bridge, > we will also have SHPC controller on ARM, so just enalbe SHPC native > hot plug. > > Cc: Shannon Zhao > Cc: Peter Maydell > Cc: "Michael S. Tsirkin" > Cc: Igor Mammedov > Signed-off-by: Heyi Guo > Signed-off-by: Heyi Guo I don't think you need two Signed-off-by lines. Besides that: Reviewed-by: Michael S. Tsirkin Pls feel free to merge through the ARM tree. > --- > hw/arm/virt-acpi-build.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index 04b62c7..7849ec5 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c > @@ -265,7 +265,12 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, > aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); > aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); > aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); > - aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL), > + > + /* > + * Allow OS control for all 5 features: > + * PCIeHotplug SHPCHotplug PME AER PCIeCapability. > + */ > + aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1F), NULL), > aml_name("CTRL"))); > > ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); > -- > 1.8.3.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:47409) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0agy-00026K-6r for qemu-devel@nongnu.org; Sun, 03 Mar 2019 18:38:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0agw-00084O-PI for qemu-devel@nongnu.org; Sun, 03 Mar 2019 18:38:48 -0500 Received: from mail-qt1-f195.google.com ([209.85.160.195]:44626) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h0agu-00082j-Qm for qemu-devel@nongnu.org; Sun, 03 Mar 2019 18:38:44 -0500 Received: by mail-qt1-f195.google.com with SMTP id d2so3393597qti.11 for ; Sun, 03 Mar 2019 15:38:43 -0800 (PST) Date: Sun, 3 Mar 2019 18:38:39 -0500 From: "Michael S. Tsirkin" Message-ID: <20190303183805-mutt-send-email-mst@kernel.org> References: <1551407310-32413-1-git-send-email-guoheyi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1551407310-32413-1-git-send-email-guoheyi@huawei.com> Subject: Re: [Qemu-devel] [PATCH] hw/arm/acpi: enable SHPC native hot plug List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Heyi Guo Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, wanghaibin.wang@huawei.com, Shannon Zhao , Peter Maydell , Igor Mammedov , Heyi Guo On Fri, Mar 01, 2019 at 10:28:30AM +0800, Heyi Guo wrote: > After the introduction of generic PCIe root port and PCIe-PCI bridge, > we will also have SHPC controller on ARM, so just enalbe SHPC native > hot plug. > > Cc: Shannon Zhao > Cc: Peter Maydell > Cc: "Michael S. Tsirkin" > Cc: Igor Mammedov > Signed-off-by: Heyi Guo > Signed-off-by: Heyi Guo I don't think you need two Signed-off-by lines. Besides that: Reviewed-by: Michael S. Tsirkin Pls feel free to merge through the ARM tree. > --- > hw/arm/virt-acpi-build.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index 04b62c7..7849ec5 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c > @@ -265,7 +265,12 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, > aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); > aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); > aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); > - aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL), > + > + /* > + * Allow OS control for all 5 features: > + * PCIeHotplug SHPCHotplug PME AER PCIeCapability. > + */ > + aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1F), NULL), > aml_name("CTRL"))); > > ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); > -- > 1.8.3.1