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Mon, 11 Mar 2019 10:59:07 -0400 Received: from mx1.redhat.com ([209.132.183.28]:28208) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h3MOO-0003TB-UX; Mon, 11 Mar 2019 10:59:05 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C81418110D; Mon, 11 Mar 2019 14:59:03 +0000 (UTC) Received: from localhost (unknown [10.43.2.182]) by smtp.corp.redhat.com (Postfix) with ESMTP id 249195DD8B; Mon, 11 Mar 2019 14:58:58 +0000 (UTC) Date: Mon, 11 Mar 2019 15:58:57 +0100 From: Igor Mammedov To: Shameer Kolothum Message-ID: <20190311155857.78c6703d@redhat.com> In-Reply-To: <20190308114218.26692-9-shameerali.kolothum.thodi@huawei.com> References: <20190308114218.26692-1-shameerali.kolothum.thodi@huawei.com> <20190308114218.26692-9-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Mon, 11 Mar 2019 14:59:03 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-arm] [PATCH v2 08/11] hw/arm/boot: Expose the PC-DIMM nodes in the DT X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, sameo@linux.intel.com, shannon.zhaosl@gmail.com, qemu-devel@nongnu.org, xuwei5@hisilicon.com, linuxarm@huawei.com, eric.auger@redhat.com, qemu-arm@nongnu.org, sebastien.boeuf@intel.com Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: Tf9dX1h4ctqX On Fri, 8 Mar 2019 11:42:15 +0000 Shameer Kolothum wrote: > This patch adds memory nodes corresponding to PC-DIMM regions. > > NVDIMM and ACPI_NVDIMM configs are not yet set for ARM so we > don't need to care about NVDIMM at this stage. > > Signed-off-by: Shameer Kolothum > Signed-off-by: Eric Auger > --- > hw/arm/boot.c | 42 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/hw/arm/boot.c b/hw/arm/boot.c > index a830655..4caaf91 100644 > --- a/hw/arm/boot.c > +++ b/hw/arm/boot.c > @@ -19,6 +19,7 @@ > #include "sysemu/numa.h" > #include "hw/boards.h" > #include "hw/loader.h" > +#include "hw/mem/memory-device.h" > #include "elf.h" > #include "sysemu/device_tree.h" > #include "qemu/config-file.h" > @@ -522,6 +523,41 @@ static void fdt_add_psci_node(void *fdt) > qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); > } > > +static int fdt_add_hotpluggable_memory_nodes(void *fdt, > + uint32_t acells, uint32_t scells) { > + MemoryDeviceInfoList *info, *info_list = qmp_memory_device_list(); > + MemoryDeviceInfo *mi; > + int ret = 0; > + > + for (info = info_list; info != NULL; info = info->next) { > + mi = info->value; > + switch (mi->type) { > + case MEMORY_DEVICE_INFO_KIND_DIMM: > + { > + PCDIMMDeviceInfo *di = mi->u.dimm.data; > + > + ret = fdt_add_memory_node(fdt, acells, di->addr, > + scells, di->size, di->node); > + if (ret) { > + fprintf(stderr, > + "couldn't add PCDIMM /memory@%"PRIx64" node\n", > + di->addr); > + goto out; > + } > + break; > + } > + default: > + fprintf(stderr, "%s memory nodes are not yet supported\n", > + MemoryDeviceInfoKind_str(mi->type)); > + ret = -ENOENT; > + goto out; > + } > + } > +out: > + qapi_free_MemoryDeviceInfoList(info_list); > + return ret; > +} > + > int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, > hwaddr addr_limit, AddressSpace *as) > { > @@ -621,6 +657,12 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, > } > } > > + rc = fdt_add_hotpluggable_memory_nodes(fdt, acells, scells); According to Eric's test, guest kernel picks this up. So it probably should be an opt-in feature to avoid conflict with ACPI definition in DSDT. > + if (rc < 0) { > + fprintf(stderr, "couldn't add hotpluggable memory nodes\n"); > + goto fail; > + } > + > rc = fdt_path_offset(fdt, "/chosen"); > if (rc < 0) { > qemu_fdt_add_subnode(fdt, "/chosen"); From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:35472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h3MOT-0006QC-PT for qemu-devel@nongnu.org; Mon, 11 Mar 2019 10:59:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h3MOS-0003X2-SG for qemu-devel@nongnu.org; Mon, 11 Mar 2019 10:59:09 -0400 Date: Mon, 11 Mar 2019 15:58:57 +0100 From: Igor Mammedov Message-ID: <20190311155857.78c6703d@redhat.com> In-Reply-To: <20190308114218.26692-9-shameerali.kolothum.thodi@huawei.com> References: <20190308114218.26692-1-shameerali.kolothum.thodi@huawei.com> <20190308114218.26692-9-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 08/11] hw/arm/boot: Expose the PC-DIMM nodes in the DT List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Shameer Kolothum Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, eric.auger@redhat.com, peter.maydell@linaro.org, shannon.zhaosl@gmail.com, sameo@linux.intel.com, sebastien.boeuf@intel.com, linuxarm@huawei.com, xuwei5@hisilicon.com On Fri, 8 Mar 2019 11:42:15 +0000 Shameer Kolothum wrote: > This patch adds memory nodes corresponding to PC-DIMM regions. > > NVDIMM and ACPI_NVDIMM configs are not yet set for ARM so we > don't need to care about NVDIMM at this stage. > > Signed-off-by: Shameer Kolothum > Signed-off-by: Eric Auger > --- > hw/arm/boot.c | 42 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/hw/arm/boot.c b/hw/arm/boot.c > index a830655..4caaf91 100644 > --- a/hw/arm/boot.c > +++ b/hw/arm/boot.c > @@ -19,6 +19,7 @@ > #include "sysemu/numa.h" > #include "hw/boards.h" > #include "hw/loader.h" > +#include "hw/mem/memory-device.h" > #include "elf.h" > #include "sysemu/device_tree.h" > #include "qemu/config-file.h" > @@ -522,6 +523,41 @@ static void fdt_add_psci_node(void *fdt) > qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); > } > > +static int fdt_add_hotpluggable_memory_nodes(void *fdt, > + uint32_t acells, uint32_t scells) { > + MemoryDeviceInfoList *info, *info_list = qmp_memory_device_list(); > + MemoryDeviceInfo *mi; > + int ret = 0; > + > + for (info = info_list; info != NULL; info = info->next) { > + mi = info->value; > + switch (mi->type) { > + case MEMORY_DEVICE_INFO_KIND_DIMM: > + { > + PCDIMMDeviceInfo *di = mi->u.dimm.data; > + > + ret = fdt_add_memory_node(fdt, acells, di->addr, > + scells, di->size, di->node); > + if (ret) { > + fprintf(stderr, > + "couldn't add PCDIMM /memory@%"PRIx64" node\n", > + di->addr); > + goto out; > + } > + break; > + } > + default: > + fprintf(stderr, "%s memory nodes are not yet supported\n", > + MemoryDeviceInfoKind_str(mi->type)); > + ret = -ENOENT; > + goto out; > + } > + } > +out: > + qapi_free_MemoryDeviceInfoList(info_list); > + return ret; > +} > + > int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, > hwaddr addr_limit, AddressSpace *as) > { > @@ -621,6 +657,12 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, > } > } > > + rc = fdt_add_hotpluggable_memory_nodes(fdt, acells, scells); According to Eric's test, guest kernel picks this up. So it probably should be an opt-in feature to avoid conflict with ACPI definition in DSDT. > + if (rc < 0) { > + fprintf(stderr, "couldn't add hotpluggable memory nodes\n"); > + goto fail; > + } > + > rc = fdt_path_offset(fdt, "/chosen"); > if (rc < 0) { > qemu_fdt_add_subnode(fdt, "/chosen");