From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu Zhao Subject: Re: [PATCH v3 3/3] arm64: mm: enable per pmd page table lock Date: Mon, 11 Mar 2019 17:11:33 -0600 Message-ID: <20190311231133.GB207964@google.com> References: <20190218231319.178224-1-yuzhao@google.com> <20190310011906.254635-1-yuzhao@google.com> <20190310011906.254635-3-yuzhao@google.com> <20190311121147.GA23361@lakrids.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20190311121147.GA23361@lakrids.cambridge.arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Mark Rutland Cc: linux-arch@vger.kernel.org, Anshuman Khandual , Peter Zijlstra , Catalin Marinas , Ard Biesheuvel , Will Deacon , linux-kernel@vger.kernel.org, Nick Piggin , Jun Yao , linux-mm@kvack.org, "Aneesh Kumar K . V" , Chintan Pandya , Joel Fernandes , "Kirill A . Shutemov" , Andrew Morton , Laura Abbott , linux-arm-kernel@lists.infradead.org List-Id: linux-arch.vger.kernel.org On Mon, Mar 11, 2019 at 12:12:28PM +0000, Mark Rutland wrote: > Hi, > > On Sat, Mar 09, 2019 at 06:19:06PM -0700, Yu Zhao wrote: > > Switch from per mm_struct to per pmd page table lock by enabling > > ARCH_ENABLE_SPLIT_PMD_PTLOCK. This provides better granularity for > > large system. > > > > I'm not sure if there is contention on mm->page_table_lock. Given > > the option comes at no cost (apart from initializing more spin > > locks), why not enable it now. > > > > We only do so when pmd is not folded, so we don't mistakenly call > > pgtable_pmd_page_ctor() on pud or p4d in pgd_pgtable_alloc(). (We > > check shift against PMD_SHIFT, which is same as PUD_SHIFT when pmd > > is folded). > > Just to check, I take it pgtable_pmd_page_ctor() is now a NOP when the > PMD is folded, and this last paragraph is stale? Yes, and will remove it. > > Signed-off-by: Yu Zhao > > --- > > arch/arm64/Kconfig | 3 +++ > > arch/arm64/include/asm/pgalloc.h | 12 +++++++++++- > > arch/arm64/include/asm/tlb.h | 5 ++++- > > 3 files changed, 18 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > > index cfbf307d6dc4..a3b1b789f766 100644 > > --- a/arch/arm64/Kconfig > > +++ b/arch/arm64/Kconfig > > @@ -872,6 +872,9 @@ config ARCH_WANT_HUGE_PMD_SHARE > > config ARCH_HAS_CACHE_LINE_SIZE > > def_bool y > > > > +config ARCH_ENABLE_SPLIT_PMD_PTLOCK > > + def_bool y if PGTABLE_LEVELS > 2 > > + > > config SECCOMP > > bool "Enable seccomp to safely compute untrusted bytecode" > > ---help--- > > diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h > > index 52fa47c73bf0..dabba4b2c61f 100644 > > --- a/arch/arm64/include/asm/pgalloc.h > > +++ b/arch/arm64/include/asm/pgalloc.h > > @@ -33,12 +33,22 @@ > > > > static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr) > > { > > - return (pmd_t *)__get_free_page(PGALLOC_GFP); > > + struct page *page; > > + > > + page = alloc_page(PGALLOC_GFP); > > + if (!page) > > + return NULL; > > + if (!pgtable_pmd_page_ctor(page)) { > > + __free_page(page); > > + return NULL; > > + } > > + return page_address(page); > > } > > > > static inline void pmd_free(struct mm_struct *mm, pmd_t *pmdp) > > { > > BUG_ON((unsigned long)pmdp & (PAGE_SIZE-1)); > > + pgtable_pmd_page_dtor(virt_to_page(pmdp)); > > free_page((unsigned long)pmdp); > > } > > It looks like arm64's existing stage-2 code is inconsistent across > alloc/free, and IIUC this change might turn that into a real problem. > Currently we allocate all levels of stage-2 table with > __get_free_page(), but free them with p?d_free(). We always miss the > ctor and always use the dtor. > > Other than that, this patch looks fine to me, but I'd feel more > comfortable if we could first fix the stage-2 code to free those stage-2 > tables without invoking the dtor. > > Anshuman, IIRC you had a patch to fix the stage-2 code to not invoke the > dtors. If so, could you please post that so that we could take it as a > preparatory patch for this series? Will do. > Thanks, > Mark. > > > diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h > > index 106fdc951b6e..4e3becfed387 100644 > > --- a/arch/arm64/include/asm/tlb.h > > +++ b/arch/arm64/include/asm/tlb.h > > @@ -62,7 +62,10 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, > > static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp, > > unsigned long addr) > > { > > - tlb_remove_table(tlb, virt_to_page(pmdp)); > > + struct page *page = virt_to_page(pmdp); > > + > > + pgtable_pmd_page_dtor(page); > > + tlb_remove_table(tlb, page); > > } > > #endif > > > > -- > > 2.21.0.360.g471c308f928-goog > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it1-f193.google.com ([209.85.166.193]:50258 "EHLO mail-it1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725861AbfCKXLj (ORCPT ); Mon, 11 Mar 2019 19:11:39 -0400 Received: by mail-it1-f193.google.com with SMTP id m137so1449376ita.0 for ; Mon, 11 Mar 2019 16:11:39 -0700 (PDT) Date: Mon, 11 Mar 2019 17:11:33 -0600 From: Yu Zhao Subject: Re: [PATCH v3 3/3] arm64: mm: enable per pmd page table lock Message-ID: <20190311231133.GB207964@google.com> References: <20190218231319.178224-1-yuzhao@google.com> <20190310011906.254635-1-yuzhao@google.com> <20190310011906.254635-3-yuzhao@google.com> <20190311121147.GA23361@lakrids.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190311121147.GA23361@lakrids.cambridge.arm.com> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Mark Rutland Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Joel Fernandes , "Kirill A . Shutemov" , Ard Biesheuvel , Chintan Pandya , Jun Yao , Laura Abbott , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org Message-ID: <20190311231133._No_QzJV_vs8tCoIO2fb4kkTbFZaHUnLZpKH--ptXtU@z> On Mon, Mar 11, 2019 at 12:12:28PM +0000, Mark Rutland wrote: > Hi, > > On Sat, Mar 09, 2019 at 06:19:06PM -0700, Yu Zhao wrote: > > Switch from per mm_struct to per pmd page table lock by enabling > > ARCH_ENABLE_SPLIT_PMD_PTLOCK. This provides better granularity for > > large system. > > > > I'm not sure if there is contention on mm->page_table_lock. Given > > the option comes at no cost (apart from initializing more spin > > locks), why not enable it now. > > > > We only do so when pmd is not folded, so we don't mistakenly call > > pgtable_pmd_page_ctor() on pud or p4d in pgd_pgtable_alloc(). (We > > check shift against PMD_SHIFT, which is same as PUD_SHIFT when pmd > > is folded). > > Just to check, I take it pgtable_pmd_page_ctor() is now a NOP when the > PMD is folded, and this last paragraph is stale? Yes, and will remove it. > > Signed-off-by: Yu Zhao > > --- > > arch/arm64/Kconfig | 3 +++ > > arch/arm64/include/asm/pgalloc.h | 12 +++++++++++- > > arch/arm64/include/asm/tlb.h | 5 ++++- > > 3 files changed, 18 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > > index cfbf307d6dc4..a3b1b789f766 100644 > > --- a/arch/arm64/Kconfig > > +++ b/arch/arm64/Kconfig > > @@ -872,6 +872,9 @@ config ARCH_WANT_HUGE_PMD_SHARE > > config ARCH_HAS_CACHE_LINE_SIZE > > def_bool y > > > > +config ARCH_ENABLE_SPLIT_PMD_PTLOCK > > + def_bool y if PGTABLE_LEVELS > 2 > > + > > config SECCOMP > > bool "Enable seccomp to safely compute untrusted bytecode" > > ---help--- > > diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h > > index 52fa47c73bf0..dabba4b2c61f 100644 > > --- a/arch/arm64/include/asm/pgalloc.h > > +++ b/arch/arm64/include/asm/pgalloc.h > > @@ -33,12 +33,22 @@ > > > > static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr) > > { > > - return (pmd_t *)__get_free_page(PGALLOC_GFP); > > + struct page *page; > > + > > + page = alloc_page(PGALLOC_GFP); > > + if (!page) > > + return NULL; > > + if (!pgtable_pmd_page_ctor(page)) { > > + __free_page(page); > > + return NULL; > > + } > > + return page_address(page); > > } > > > > static inline void pmd_free(struct mm_struct *mm, pmd_t *pmdp) > > { > > BUG_ON((unsigned long)pmdp & (PAGE_SIZE-1)); > > + pgtable_pmd_page_dtor(virt_to_page(pmdp)); > > free_page((unsigned long)pmdp); > > } > > It looks like arm64's existing stage-2 code is inconsistent across > alloc/free, and IIUC this change might turn that into a real problem. > Currently we allocate all levels of stage-2 table with > __get_free_page(), but free them with p?d_free(). We always miss the > ctor and always use the dtor. > > Other than that, this patch looks fine to me, but I'd feel more > comfortable if we could first fix the stage-2 code to free those stage-2 > tables without invoking the dtor. > > Anshuman, IIRC you had a patch to fix the stage-2 code to not invoke the > dtors. If so, could you please post that so that we could take it as a > preparatory patch for this series? Will do. > Thanks, > Mark. > > > diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h > > index 106fdc951b6e..4e3becfed387 100644 > > --- a/arch/arm64/include/asm/tlb.h > > +++ b/arch/arm64/include/asm/tlb.h > > @@ -62,7 +62,10 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, > > static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp, > > unsigned long addr) > > { > > - tlb_remove_table(tlb, virt_to_page(pmdp)); > > + struct page *page = virt_to_page(pmdp); > > + > > + pgtable_pmd_page_dtor(page); > > + tlb_remove_table(tlb, page); > > } > > #endif > > > > -- > > 2.21.0.360.g471c308f928-goog > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.5 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FSL_HELO_FAKE, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27FFFC43381 for ; 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Mon, 11 Mar 2019 16:11:38 -0700 (PDT) Received: from google.com ([2620:15c:183:0:a0c3:519e:9276:fc96]) by smtp.gmail.com with ESMTPSA id x24sm2849861ioa.50.2019.03.11.16.11.37 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 11 Mar 2019 16:11:37 -0700 (PDT) Date: Mon, 11 Mar 2019 17:11:33 -0600 From: Yu Zhao To: Mark Rutland Subject: Re: [PATCH v3 3/3] arm64: mm: enable per pmd page table lock Message-ID: <20190311231133.GB207964@google.com> References: <20190218231319.178224-1-yuzhao@google.com> <20190310011906.254635-1-yuzhao@google.com> <20190310011906.254635-3-yuzhao@google.com> <20190311121147.GA23361@lakrids.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190311121147.GA23361@lakrids.cambridge.arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190311_161139_361107_C6641A75 X-CRM114-Status: GOOD ( 30.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Anshuman Khandual , Peter Zijlstra , Catalin Marinas , Ard Biesheuvel , Will Deacon , linux-kernel@vger.kernel.org, Nick Piggin , Jun Yao , linux-mm@kvack.org, "Aneesh Kumar K . V" , Chintan Pandya , Joel Fernandes , "Kirill A . Shutemov" , Andrew Morton , Laura Abbott , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Mar 11, 2019 at 12:12:28PM +0000, Mark Rutland wrote: > Hi, > > On Sat, Mar 09, 2019 at 06:19:06PM -0700, Yu Zhao wrote: > > Switch from per mm_struct to per pmd page table lock by enabling > > ARCH_ENABLE_SPLIT_PMD_PTLOCK. This provides better granularity for > > large system. > > > > I'm not sure if there is contention on mm->page_table_lock. Given > > the option comes at no cost (apart from initializing more spin > > locks), why not enable it now. > > > > We only do so when pmd is not folded, so we don't mistakenly call > > pgtable_pmd_page_ctor() on pud or p4d in pgd_pgtable_alloc(). (We > > check shift against PMD_SHIFT, which is same as PUD_SHIFT when pmd > > is folded). > > Just to check, I take it pgtable_pmd_page_ctor() is now a NOP when the > PMD is folded, and this last paragraph is stale? Yes, and will remove it. > > Signed-off-by: Yu Zhao > > --- > > arch/arm64/Kconfig | 3 +++ > > arch/arm64/include/asm/pgalloc.h | 12 +++++++++++- > > arch/arm64/include/asm/tlb.h | 5 ++++- > > 3 files changed, 18 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > > index cfbf307d6dc4..a3b1b789f766 100644 > > --- a/arch/arm64/Kconfig > > +++ b/arch/arm64/Kconfig > > @@ -872,6 +872,9 @@ config ARCH_WANT_HUGE_PMD_SHARE > > config ARCH_HAS_CACHE_LINE_SIZE > > def_bool y > > > > +config ARCH_ENABLE_SPLIT_PMD_PTLOCK > > + def_bool y if PGTABLE_LEVELS > 2 > > + > > config SECCOMP > > bool "Enable seccomp to safely compute untrusted bytecode" > > ---help--- > > diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h > > index 52fa47c73bf0..dabba4b2c61f 100644 > > --- a/arch/arm64/include/asm/pgalloc.h > > +++ b/arch/arm64/include/asm/pgalloc.h > > @@ -33,12 +33,22 @@ > > > > static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr) > > { > > - return (pmd_t *)__get_free_page(PGALLOC_GFP); > > + struct page *page; > > + > > + page = alloc_page(PGALLOC_GFP); > > + if (!page) > > + return NULL; > > + if (!pgtable_pmd_page_ctor(page)) { > > + __free_page(page); > > + return NULL; > > + } > > + return page_address(page); > > } > > > > static inline void pmd_free(struct mm_struct *mm, pmd_t *pmdp) > > { > > BUG_ON((unsigned long)pmdp & (PAGE_SIZE-1)); > > + pgtable_pmd_page_dtor(virt_to_page(pmdp)); > > free_page((unsigned long)pmdp); > > } > > It looks like arm64's existing stage-2 code is inconsistent across > alloc/free, and IIUC this change might turn that into a real problem. > Currently we allocate all levels of stage-2 table with > __get_free_page(), but free them with p?d_free(). We always miss the > ctor and always use the dtor. > > Other than that, this patch looks fine to me, but I'd feel more > comfortable if we could first fix the stage-2 code to free those stage-2 > tables without invoking the dtor. > > Anshuman, IIRC you had a patch to fix the stage-2 code to not invoke the > dtors. If so, could you please post that so that we could take it as a > preparatory patch for this series? Will do. > Thanks, > Mark. > > > diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h > > index 106fdc951b6e..4e3becfed387 100644 > > --- a/arch/arm64/include/asm/tlb.h > > +++ b/arch/arm64/include/asm/tlb.h > > @@ -62,7 +62,10 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, > > static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp, > > unsigned long addr) > > { > > - tlb_remove_table(tlb, virt_to_page(pmdp)); > > + struct page *page = virt_to_page(pmdp); > > + > > + pgtable_pmd_page_dtor(page); > > + tlb_remove_table(tlb, page); > > } > > #endif > > > > -- > > 2.21.0.360.g471c308f928-goog > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel