From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [PATCHv2,1/5] Documentation: dt: edac: Fix Stratix10 IRQ bindings From: Rob Herring Message-Id: <20190312160057.GA31306@bogus> Date: Tue, 12 Mar 2019 11:00:57 -0500 To: thor.thayer@linux.intel.com Cc: bp@alien8.de, dinguyen@kernel.org, mark.rutland@arm.com, mchehab@kernel.org, devicetree@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org List-ID: T24gV2VkLCBGZWIgMjcsIDIwMTkgYXQgMTE6Mjc6MjFBTSAtMDYwMCwgdGhvci50aGF5ZXJAbGlu dXguaW50ZWwuY29tIHdyb3RlOgo+IEZyb206IFRob3IgVGhheWVyIDx0aG9yLnRoYXllckBsaW51 eC5pbnRlbC5jb20+Cj4gCj4gRml4IFN0cmF0aXgxMCBFQ0MgYmluZGluZ3MgdG8gc3BlY2lmeSBv bmx5IHRoZSBzaW5nbGUKPiBiaXQgZXJyb3IuIE9uIFN0cmF0aXgxMCBkb3VibGUgYml0IGVycm9y cyBhcmUgaGFuZGxlZAo+IGFzIFNFcnJvcnMgaW5zdGVhZCBvZiBpbnRlcnJ1cHRzLgo+IEluZGlj YXRlIHRoZSBkaWZmZXJlbmNlcyBiZXR3ZWVuIHRoZSBBUk02NCBhbmQgQVJNMzIKPiBFREFDIGFy Y2hpdGVjdHVyZSBpbiB0aGUgYmluZGluZ3MuCj4gCj4gU2lnbmVkLW9mZi1ieTogVGhvciBUaGF5 ZXIgPHRob3IudGhheWVyQGxpbnV4LmludGVsLmNvbT4KPiAtLS0KPiB2MiBObyBjaGFuZ2UKPiAt LS0KPiAgLi4uL2RldmljZXRyZWUvYmluZGluZ3MvZWRhYy9zb2NmcGdhLWVjY21nci50eHQgICAg fCAyMyArKysrKysrKysrKysrKystLS0tLS0tCj4gIDEgZmlsZSBjaGFuZ2VkLCAxNiBpbnNlcnRp b25zKCspLCA3IGRlbGV0aW9ucygtKQo+IAo+IGRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2Rl dmljZXRyZWUvYmluZGluZ3MvZWRhYy9zb2NmcGdhLWVjY21nci50eHQgYi9Eb2N1bWVudGF0aW9u L2RldmljZXRyZWUvYmluZGluZ3MvZWRhYy9zb2NmcGdhLWVjY21nci50eHQKPiBpbmRleCA1NjI2 NTYwYTZjZmQuLmEwYWM1MGUxNTkxMiAxMDA2NDQKPiAtLS0gYS9Eb2N1bWVudGF0aW9uL2Rldmlj ZXRyZWUvYmluZGluZ3MvZWRhYy9zb2NmcGdhLWVjY21nci50eHQKPiArKysgYi9Eb2N1bWVudGF0 aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZWRhYy9zb2NmcGdhLWVjY21nci50eHQKPiBAQCAtMjM2 LDMzICsyMzYsNDIgQEAgU3RyYXRpeDEwIFNvQ0ZQR0EgRUNDIE1hbmFnZXIKPiAgVGhlIFN0cmF0 aXgxMCBTb0MgRUNDIE1hbmFnZXIgaGFuZGxlcyB0aGUgSVJRcyBmb3IgZWFjaCBwZXJpcGhlcmFs Cj4gIGluIGEgc2hhcmVkIHJlZ2lzdGVyIHNpbWlsYXIgdG8gdGhlIEFycmlhMTAuIEhvd2V2ZXIs IEVDQyByZXF1aXJlcwo+ICBhY2Nlc3MgdG8gcmVnaXN0ZXJzIHRoYXQgY2FuIG9ubHkgYmUgcmVh ZCBmcm9tIFNlY3VyZSBNb25pdG9yIHdpdGgKPiAtU01DIGNhbGxzLiBUaGVyZWZvcmUgdGhlIGRl dmljZSB0cmVlIGlzIHNsaWdodGx5IGRpZmZlcmVudC4KPiArU01DIGNhbGxzLiBUaGVyZWZvcmUg dGhlIGRldmljZSB0cmVlIGlzIHNsaWdodGx5IGRpZmZlcmVudC4gTm90ZSB0aGF0Cj4gK29ubHkg MSBpbnRlcnJ1cHQgaXMgc2VudCBiZWNhdXNlIHRoZSBkb3VibGUgYml0IGVycm9ycyBhcmUgdHJl YXRlZCBhcwo+ICtTRXJyb3JzIGluc3RlYWQgb2YgSVJRLgo+ICAKPiAgUmVxdWlyZWQgUHJvcGVy dGllczoKPiAgLSBjb21wYXRpYmxlIDogU2hvdWxkIGJlICJhbHRyLHNvY2ZwZ2EtczEwLWVjYy1t YW5hZ2VyIgo+IC0tIGludGVycnVwdHMgOiBTaG91bGQgYmUgc2luZ2xlIGJpdCBlcnJvciBpbnRl cnJ1cHQsIHRoZW4gZG91YmxlIGJpdCBlcnJvcgo+IC0JaW50ZXJydXB0Lgo+ICstIGFsdHIsc3lz Z3Itc3lzY29uIDogcGhhbmRsZSB0byBTdHJhdGl4MTAgU3lzdGVtIE1hbmFnZXIgQmxvY2sKPiAr CSAgICAgICAgICAgICAgY29udGFpbmluZyB0aGUgRUNDIG1hbmFnZXIgcmVnaXN0ZXJzLgoKU2Vl bXMgdGhpcyB3YXMgYWxyZWFkeSBpbiB1c2UsIGJ1dCB3aHkgbm90IGp1c3QgbWFrZSB0aGlzIG5v ZGUgYSBjaGlsZCAKb2YgdGhlIFN5c3RlbSBNYW5hZ2VyIEJsb2NrIGFuZCByZW1vdmUgdGhpcyBw aGFuZGxlPwoKPiArLSBpbnRlcnJ1cHRzIDogU2hvdWxkIGJlIHNpbmdsZSBiaXQgZXJyb3IgaW50 ZXJydXB0Lgo+ICAtIGludGVycnVwdC1jb250cm9sbGVyIDogYm9vbGVhbiBpbmRpY2F0b3IgdGhh dCBFQ0MgTWFuYWdlciBpcyBhbiBpbnRlcnJ1cHQgY29udHJvbGxlcgo+ICAtICNpbnRlcnJ1cHQt Y2VsbHMgOiBtdXN0IGJlIHNldCB0byAyLgo+ICstICNhZGRyZXNzLWNlbGxzOiBtdXN0IGJlIDEK PiArLSAjc2l6ZS1jZWxsczogbXVzdCBiZSAxCj4gKy0gcmFuZ2VzIDogc3RhbmRhcmQgZGVmaW5p dGlvbiwgc2hvdWxkIHRyYW5zbGF0ZSBmcm9tIGxvY2FsIGFkZHJlc3Nlcwo+ICAKPiAgU3ViY29t cG9uZW50czoKPiAgCj4gIFNEUkFNIEVDQwo+ICBSZXF1aXJlZCBQcm9wZXJ0aWVzOgo+ICAtIGNv bXBhdGlibGUgOiBTaG91bGQgYmUgImFsdHIsc2RyYW0tZWRhYy1zMTAiCj4gLS0gaW50ZXJydXB0 cyA6IFNob3VsZCBiZSBzaW5nbGUgYml0IGVycm9yIGludGVycnVwdCwgdGhlbiBkb3VibGUgYml0 IGVycm9yCj4gLQlpbnRlcnJ1cHQsIGluIHRoaXMgb3JkZXIuCj4gKy0gaW50ZXJydXB0cyA6IFNo b3VsZCBiZSBzaW5nbGUgYml0IGVycm9yIGludGVycnVwdC4KPiAgCj4gIEV4YW1wbGU6Cj4gIAo+ ICAJZWNjbWdyIHsKPiAgCQljb21wYXRpYmxlID0gImFsdHIsc29jZnBnYS1zMTAtZWNjLW1hbmFn ZXIiOwo+IC0JCWludGVycnVwdHMgPSA8MCAxNSA0PiwgPDAgOTUgND47Cj4gKwkJYWx0cixzeXNt Z3Itc3lzY29uID0gPCZzeXNtZ3I+Owo+ICsJCSNhZGRyZXNzLWNlbGxzID0gPDE+Owo+ICsJCSNz aXplLWNlbGxzID0gPDE+Owo+ICsJCWludGVycnVwdHMgPSA8MCAxNSA0PjsKPiAgCQlpbnRlcnJ1 cHQtY29udHJvbGxlcjsKPiAgCQkjaW50ZXJydXB0LWNlbGxzID0gPDI+Owo+ICsJCXJhbmdlczsK PiAgCj4gIAkJc2RyYW1lZGFjIHsKPiAgCQkJY29tcGF0aWJsZSA9ICJhbHRyLHNkcmFtLWVkYWMt czEwIjsKPiAtCQkJaW50ZXJydXB0cyA9IDwxNiA0PiwgPDQ4IDQ+Owo+ICsJCQlpbnRlcnJ1cHRz ID0gPDE2IElSUV9UWVBFX0xFVkVMX0hJR0g+Owo+ICAJCX07Cj4gIAl9Owo+IC0tIAo+IDIuNy40 Cj4K From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCHv2 1/5] Documentation: dt: edac: Fix Stratix10 IRQ bindings Date: Tue, 12 Mar 2019 11:00:57 -0500 Message-ID: <20190312160057.GA31306@bogus> References: <1551288445-22335-1-git-send-email-thor.thayer@linux.intel.com> <1551288445-22335-2-git-send-email-thor.thayer@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1551288445-22335-2-git-send-email-thor.thayer@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org To: thor.thayer@linux.intel.com Cc: bp@alien8.de, dinguyen@kernel.org, mark.rutland@arm.com, mchehab@kernel.org, devicetree@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org On Wed, Feb 27, 2019 at 11:27:21AM -0600, thor.thayer@linux.intel.com wrote: > From: Thor Thayer > > Fix Stratix10 ECC bindings to specify only the single > bit error. On Stratix10 double bit errors are handled > as SErrors instead of interrupts. > Indicate the differences between the ARM64 and ARM32 > EDAC architecture in the bindings. > > Signed-off-by: Thor Thayer > --- > v2 No change > --- > .../devicetree/bindings/edac/socfpga-eccmgr.txt | 23 +++++++++++++++------- > 1 file changed, 16 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt > index 5626560a6cfd..a0ac50e15912 100644 > --- a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt > +++ b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt > @@ -236,33 +236,42 @@ Stratix10 SoCFPGA ECC Manager > The Stratix10 SoC ECC Manager handles the IRQs for each peripheral > in a shared register similar to the Arria10. However, ECC requires > access to registers that can only be read from Secure Monitor with > -SMC calls. Therefore the device tree is slightly different. > +SMC calls. Therefore the device tree is slightly different. Note that > +only 1 interrupt is sent because the double bit errors are treated as > +SErrors instead of IRQ. > > Required Properties: > - compatible : Should be "altr,socfpga-s10-ecc-manager" > -- interrupts : Should be single bit error interrupt, then double bit error > - interrupt. > +- altr,sysgr-syscon : phandle to Stratix10 System Manager Block > + containing the ECC manager registers. Seems this was already in use, but why not just make this node a child of the System Manager Block and remove this phandle? > +- interrupts : Should be single bit error interrupt. > - interrupt-controller : boolean indicator that ECC Manager is an interrupt controller > - #interrupt-cells : must be set to 2. > +- #address-cells: must be 1 > +- #size-cells: must be 1 > +- ranges : standard definition, should translate from local addresses > > Subcomponents: > > SDRAM ECC > Required Properties: > - compatible : Should be "altr,sdram-edac-s10" > -- interrupts : Should be single bit error interrupt, then double bit error > - interrupt, in this order. > +- interrupts : Should be single bit error interrupt. > > Example: > > eccmgr { > compatible = "altr,socfpga-s10-ecc-manager"; > - interrupts = <0 15 4>, <0 95 4>; > + altr,sysmgr-syscon = <&sysmgr>; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupts = <0 15 4>; > interrupt-controller; > #interrupt-cells = <2>; > + ranges; > > sdramedac { > compatible = "altr,sdram-edac-s10"; > - interrupts = <16 4>, <48 4>; > + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; > }; > }; > -- > 2.7.4 >