From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28D3BC43381 for ; Tue, 12 Mar 2019 17:15:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E30B42184C for ; Tue, 12 Mar 2019 17:15:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1552410945; bh=uHnUdrcP7OLYsT9Ovn1mLx20Mov/N3nXiKXmsaKMSgU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=sDsXvfVAtuPUYJ89+r/C99EBh88QBYWPG8zKOJ60d9HjvloTXWoivzRy7xNV43euy QZpyrMVFmKYpdHUXFAzCROvsmrutZLD0kDlABx9CQ4P0xWsG4UCLUt+6saUyk/BZjs +CjfPq/lEdhXN8CJN9PPEvreYGaYufSKJ9ersOW8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728849AbfCLRPn (ORCPT ); Tue, 12 Mar 2019 13:15:43 -0400 Received: from mail.kernel.org ([198.145.29.99]:54448 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728248AbfCLROz (ORCPT ); Tue, 12 Mar 2019 13:14:55 -0400 Received: from localhost (unknown [104.133.8.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 22A3A21741; Tue, 12 Mar 2019 17:14:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1552410894; bh=uHnUdrcP7OLYsT9Ovn1mLx20Mov/N3nXiKXmsaKMSgU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ttWt8x3jqj47/MVRM2eQlgQPMF+6IQ48vNeEKDyGk0VRw944MCSep4xP4hlZq+/ET xi2Ok4zhKrAHO6jSvvmZsLFVg8vIc//i21WG+KSmI5DUQmZenkPgoY+JEI06CsZdXX Q8dD+OddTg0RRhsgcwYvzHDYhUPoRdBZ8JifFaXU= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Lubomir Rintel , Pavel Machek , Marc Zyngier , Sasha Levin Subject: [PATCH 4.19 084/149] irqchip/mmp: Only touch the PJ4 IRQ & FIQ bits on enable/disable Date: Tue, 12 Mar 2019 10:08:22 -0700 Message-Id: <20190312170356.773598107@linuxfoundation.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190312170349.421581206@linuxfoundation.org> References: <20190312170349.421581206@linuxfoundation.org> User-Agent: quilt/0.65 X-stable: review X-Patchwork-Hint: ignore MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 4.19-stable review patch. If anyone has any objections, please let me know. ------------------ [ Upstream commit 2380a22b60ce6f995eac806e69c66e397b59d045 ] Resetting bit 4 disables the interrupt delivery to the "secure processor" core. This breaks the keyboard on a OLPC XO 1.75 laptop, where the firmware running on the "secure processor" bit-bangs the PS/2 protocol over the GPIO lines. It is not clear what the rest of the bits are and Marvell was unhelpful when asked for documentation. Aside from the SP bit, there are probably priority bits. Leaving the unknown bits as the firmware set them up seems to be a wiser course of action compared to just turning them off. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek [maz: fixed-up subject and commit message] Signed-off-by: Marc Zyngier Signed-off-by: Sasha Levin --- drivers/irqchip/irq-mmp.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c index 25f32e1d7764..3496b61a312a 100644 --- a/drivers/irqchip/irq-mmp.c +++ b/drivers/irqchip/irq-mmp.c @@ -34,6 +34,9 @@ #define SEL_INT_PENDING (1 << 6) #define SEL_INT_NUM_MASK 0x3f +#define MMP2_ICU_INT_ROUTE_PJ4_IRQ (1 << 5) +#define MMP2_ICU_INT_ROUTE_PJ4_FIQ (1 << 6) + struct icu_chip_data { int nr_irqs; unsigned int virq_base; @@ -190,7 +193,8 @@ static const struct mmp_intc_conf mmp_conf = { static const struct mmp_intc_conf mmp2_conf = { .conf_enable = 0x20, .conf_disable = 0x0, - .conf_mask = 0x7f, + .conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ | + MMP2_ICU_INT_ROUTE_PJ4_FIQ, }; static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs) -- 2.19.1