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Thu, 14 Mar 2019 05:30:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h4MVa-0003vH-2K for qemu-devel@nongnu.org; Thu, 14 Mar 2019 05:18:39 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46882) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h4MVY-0003u8-Lj; Thu, 14 Mar 2019 05:18:36 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 902BDC058CAD; Thu, 14 Mar 2019 09:18:35 +0000 (UTC) Received: from localhost (unknown [10.43.2.182]) by smtp.corp.redhat.com (Postfix) with ESMTP id D003C4C4; Thu, 14 Mar 2019 09:18:31 +0000 (UTC) Date: Thu, 14 Mar 2019 10:18:30 +0100 From: Igor Mammedov To: Wei Yang Message-ID: <20190314101830.6e10d4d5@redhat.com> In-Reply-To: <20190313213137.acncaz7duosjybnf@master> References: <20190313044253.31988-1-richardw.yang@linux.intel.com> <20190313044253.31988-4-richardw.yang@linux.intel.com> <20190313132300.3f56a5ca@redhat.com> <20190313133359.h2njohyijgvkcbtv@master> <20190313170943.5384f5cf@redhat.com> <20190313213137.acncaz7duosjybnf@master> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Thu, 14 Mar 2019 09:18:35 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-devel] [RFC PATCH 3/3] hw/acpi: Extract build_mcfg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mst@redhat.com, qemu-devel@nongnu.org, shannon.zhaosl@gmail.com, qemu-arm@nongnu.org, Wei Yang Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-devel" X-TUID: AH93S8ENZCN5 On Wed, 13 Mar 2019 21:31:37 +0000 Wei Yang wrote: > On Wed, Mar 13, 2019 at 05:09:43PM +0100, Igor Mammedov wrote: > >On Wed, 13 Mar 2019 13:33:59 +0000 > >Wei Yang wrote: > > > >> On Wed, Mar 13, 2019 at 01:23:00PM +0100, Igor Mammedov wrote: > >> >On Wed, 13 Mar 2019 12:42:53 +0800 > >> >Wei Yang wrote: > >> > > >> >> Now we have two identical build_mcfg function. > >> >> > >> >> Extract them to aml-build.c. > >> >> > >> >> Signed-off-by: Wei Yang > >> >> --- > >> >> hw/acpi/aml-build.c | 30 ++++++++++++++++++++++++++++++ > >> >> hw/arm/virt-acpi-build.c | 16 ---------------- > >> >> hw/i386/acpi-build.c | 31 +------------------------------ > >> >> include/hw/acpi/aml-build.h | 1 + > >> >> 4 files changed, 32 insertions(+), 46 deletions(-) > >> >> > >> >> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c > >> >> index 555c24f21d..58d3b8f31d 100644 > >> >> --- a/hw/acpi/aml-build.c > >> >> +++ b/hw/acpi/aml-build.c > >> > > >> >I don't like polluting aml-build.c with PCI stuff, > >> >we have a lot of PCI related code that needs generalizing > >> >lets create a new file for that, something like > >> >hw/acpi/pci.c + include/hw/acpi/pci.h > >> > > >> >> @@ -25,6 +25,7 @@ > >> >> #include "qemu/bswap.h" > >> >> #include "qemu/bitops.h" > >> >> #include "sysemu/numa.h" > >> >> +#include "hw/pci/pcie_host.h" > >> >> > >> >> static GArray *build_alloc_array(void) > >> >> { > >> >> @@ -1870,3 +1871,32 @@ build_hdr: > >> >> build_header(linker, tbl, (void *)(tbl->data + fadt_start), > >> >> "FACP", tbl->len - fadt_start, f->rev, oem_id, oem_table_id); > >> >> } > >> >> + > >> >> +void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info) > >> >> +{ > >> >> + AcpiTableMcfg *mcfg; > >> >> + const char *sig; > >> >> + int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]); > >> >> + > >> >> + mcfg = acpi_data_push(table_data, len); > >> >> + mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); > >> >> + /* Only a single allocation so no need to play with segments */ > >> >> + mcfg->allocation[0].pci_segment = cpu_to_le16(0); > >> >> + mcfg->allocation[0].start_bus_number = 0; > >> >> + mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); > >> > > >> >> + /* > >> >> + * MCFG is used for ECAM which can be enabled or disabled by guest. > >> >> + * To avoid table size changes (which create migration issues), > >> >> + * always create the table even if there are no allocations, > >> >> + * but set the signature to a reserved value in this case. > >> >> + * ACPI spec requires OSPMs to ignore such tables. > >> >> + */ > >> >> + if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { > >> >> + /* Reserved signature: ignored by OSPM */ > >> >> + sig = "QEMU"; > >> >> + } else { > >> >> + sig = "MCFG"; > >> >> + } > >> >I'd leave these hack at acpi-build.c, just push it up call chain. > >> > >> Assign sig in acpi-build.c and pass it to build_mcfg()? > >nope, see more below > > > > > >> >More over we don't really need it since resizeable memory region was introduced. > >> > > >> >So we need to keep table_blob size only for legacy usecase (pre resizable) > >> >and for that just padding table_blob on required size would be sufficient, > >> >there is no need to create dummy QEMU table. > >> >As for newer machines (since resizeable memory region) we don't need to > >> >do even that i.e. just skip table generation altogether if guest disabled it. > >> > > >> > >> I am lost at this place. > >> > >> sig is a part of ACPI table header, you mean the sig is not necessary to > >> be set in ACPI table header? > >> > >> "skip table generation" means remove build_header() in build_mcfg()? > >I mean do not call build_mcfg() at all when you don't have to. > > > >And when you need to keep table_blob the same size (for old machines) > >using acpi_data_push() to reserve space instead of build_mcfg(sig="QEMU") > >might just work as well. it's still hack but it can live in x86 specific > >acpi_build() keeping build_mcfg() generic. > > > > Seems got your idea. > > >As for defining what to use as criteria to decide when we need to keep > >table_blob size the same, I don't remember history of it, so I'd suggest > >to look at commit a1666142, study history of acpi_ram_update() and > >legacy_acpi_table_size to figure out since which machine type one doesn't > >have to keep table_blob size the same. > > > > OK, let me study the history first. > > BTW, the legacy here is hardware specification level or qemu software > design level? it's QEMU only, you need to find a version of QEMU (machine type) which didn't have re-sizable MemoryRegion and the next version most likely would have a knob somewhere in machine class definition saying that we don't care about sizes anymore or care about sizes only for previous machine types.