Re: [PATCH v4 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type

[kbuild test robot <lkp@intel.com>]

Hi Praveen,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20190306]
[cannot apply to v5.0]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Ankit-Navik/drm-i915-Context-aware-user-agnostic-EU-Slice-Sub-slice-control-within-kernel/20190314-181342
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
        # apt-get install sparse
        make ARCH=x86_64 allmodconfig
        make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'


sparse warnings: (new ones prefixed by >>)

   include/uapi/linux/perf_event.h:147:56: sparse: cast truncates bits from constant value (8000000000000000 becomes 0)
>> drivers/gpu/drm/i915/intel_device_info.c:858:28: sparse: incorrect type in assignment (different modifiers) @@    expected struct i915_sseu_optimum_config *opt_config @@    got structstruct i915_sseu_optimum_config *opt_config @@
   drivers/gpu/drm/i915/intel_device_info.c:858:28:    expected struct i915_sseu_optimum_config *opt_config
   drivers/gpu/drm/i915/intel_device_info.c:858:28:    got struct i915_sseu_optimum_config const *<noident>
   drivers/gpu/drm/i915/intel_device_info.c:869:36: sparse: incorrect type in assignment (different modifiers) @@    expected struct i915_sseu_optimum_config *opt_config @@    got structstruct i915_sseu_optimum_config *opt_config @@
   drivers/gpu/drm/i915/intel_device_info.c:869:36:    expected struct i915_sseu_optimum_config *opt_config
   drivers/gpu/drm/i915/intel_device_info.c:869:36:    got struct i915_sseu_optimum_config const *<noident>
   drivers/gpu/drm/i915/intel_device_info.c:874:36: sparse: incorrect type in assignment (different modifiers) @@    expected struct i915_sseu_optimum_config *opt_config @@    got structstruct i915_sseu_optimum_config *opt_config @@
   drivers/gpu/drm/i915/intel_device_info.c:874:36:    expected struct i915_sseu_optimum_config *opt_config
   drivers/gpu/drm/i915/intel_device_info.c:874:36:    got struct i915_sseu_optimum_config const *<noident>

vim +858 drivers/gpu/drm/i915/intel_device_info.c

   730	
   731	/**
   732	 * intel_device_info_runtime_init - initialize runtime info
   733	 * @dev_priv: the i915 device
   734	 *
   735	 * Determine various intel_device_info fields at runtime.
   736	 *
   737	 * Use it when either:
   738	 *   - it's judged too laborious to fill n static structures with the limit
   739	 *     when a simple if statement does the job,
   740	 *   - run-time checks (eg read fuse/strap registers) are needed.
   741	 *
   742	 * This function needs to be called:
   743	 *   - after the MMIO has been setup as we are reading registers,
   744	 *   - after the PCH has been detected,
   745	 *   - before the first usage of the fields it can tweak.
   746	 */
   747	void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
   748	{
   749		struct intel_device_info *info = mkwrite_device_info(dev_priv);
   750		struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
   751		enum pipe pipe;
   752		struct i915_sseu_optimum_config *opt_config = NULL;
   753	
   754		if (INTEL_GEN(dev_priv) >= 10) {
   755			for_each_pipe(dev_priv, pipe)
   756				runtime->num_scalers[pipe] = 2;
   757		} else if (IS_GEN(dev_priv, 9)) {
   758			runtime->num_scalers[PIPE_A] = 2;
   759			runtime->num_scalers[PIPE_B] = 2;
   760			runtime->num_scalers[PIPE_C] = 1;
   761		}
   762	
   763		BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
   764	
   765		if (IS_GEN(dev_priv, 11))
   766			for_each_pipe(dev_priv, pipe)
   767				runtime->num_sprites[pipe] = 6;
   768		else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
   769			for_each_pipe(dev_priv, pipe)
   770				runtime->num_sprites[pipe] = 3;
   771		else if (IS_BROXTON(dev_priv)) {
   772			/*
   773			 * Skylake and Broxton currently don't expose the topmost plane as its
   774			 * use is exclusive with the legacy cursor and we only want to expose
   775			 * one of those, not both. Until we can safely expose the topmost plane
   776			 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
   777			 * we don't expose the topmost plane at all to prevent ABI breakage
   778			 * down the line.
   779			 */
   780	
   781			runtime->num_sprites[PIPE_A] = 2;
   782			runtime->num_sprites[PIPE_B] = 2;
   783			runtime->num_sprites[PIPE_C] = 1;
   784		} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
   785			for_each_pipe(dev_priv, pipe)
   786				runtime->num_sprites[pipe] = 2;
   787		} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
   788			for_each_pipe(dev_priv, pipe)
   789				runtime->num_sprites[pipe] = 1;
   790		}
   791	
   792		if (i915_modparams.disable_display) {
   793			DRM_INFO("Display disabled (module parameter)\n");
   794			info->num_pipes = 0;
   795		} else if (HAS_DISPLAY(dev_priv) &&
   796			   (IS_GEN_RANGE(dev_priv, 7, 8)) &&
   797			   HAS_PCH_SPLIT(dev_priv)) {
   798			u32 fuse_strap = I915_READ(FUSE_STRAP);
   799			u32 sfuse_strap = I915_READ(SFUSE_STRAP);
   800	
   801			/*
   802			 * SFUSE_STRAP is supposed to have a bit signalling the display
   803			 * is fused off. Unfortunately it seems that, at least in
   804			 * certain cases, fused off display means that PCH display
   805			 * reads don't land anywhere. In that case, we read 0s.
   806			 *
   807			 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
   808			 * should be set when taking over after the firmware.
   809			 */
   810			if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
   811			    sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
   812			    (HAS_PCH_CPT(dev_priv) &&
   813			     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
   814				DRM_INFO("Display fused off, disabling\n");
   815				info->num_pipes = 0;
   816			} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
   817				DRM_INFO("PipeC fused off\n");
   818				info->num_pipes -= 1;
   819			}
   820		} else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
   821			u32 dfsm = I915_READ(SKL_DFSM);
   822			u8 disabled_mask = 0;
   823			bool invalid;
   824			int num_bits;
   825	
   826			if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
   827				disabled_mask |= BIT(PIPE_A);
   828			if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
   829				disabled_mask |= BIT(PIPE_B);
   830			if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
   831				disabled_mask |= BIT(PIPE_C);
   832	
   833			num_bits = hweight8(disabled_mask);
   834	
   835			switch (disabled_mask) {
   836			case BIT(PIPE_A):
   837			case BIT(PIPE_B):
   838			case BIT(PIPE_A) | BIT(PIPE_B):
   839			case BIT(PIPE_A) | BIT(PIPE_C):
   840				invalid = true;
   841				break;
   842			default:
   843				invalid = false;
   844			}
   845	
   846			if (num_bits > info->num_pipes || invalid)
   847				DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
   848					  disabled_mask);
   849			else
   850				info->num_pipes -= num_bits;
   851		}
   852	
   853		/* Initialize slice/subslice/EU info */
   854		if (IS_HASWELL(dev_priv))
   855			haswell_sseu_info_init(dev_priv);
   856		else if (IS_CHERRYVIEW(dev_priv)) {
   857			cherryview_sseu_info_init(dev_priv);
 > 858			opt_config = chv_config;
   859			BUILD_BUG_ON(ARRAY_SIZE(chv_config) != LOAD_TYPE_LAST);
   860		}
   861		else if (IS_BROADWELL(dev_priv))
   862			broadwell_sseu_info_init(dev_priv);
   863		else if (IS_GEN(dev_priv, 9)) {
   864			gen9_sseu_info_init(dev_priv);
   865	
   866			switch (info->gt) {
   867			default: /* fall through */
   868			case 2:
   869				opt_config = kbl_gt2_config;
   870				BUILD_BUG_ON(ARRAY_SIZE(kbl_gt2_config)
   871							!= LOAD_TYPE_LAST);
   872			break;
   873			case 3:
   874				opt_config = kbl_gt3_config;
   875				BUILD_BUG_ON(ARRAY_SIZE(kbl_gt3_config)
   876							!= LOAD_TYPE_LAST);
   877			break;
   878			}
   879		}
   880		else if (IS_GEN(dev_priv, 10))
   881			gen10_sseu_info_init(dev_priv);
   882		else if (INTEL_GEN(dev_priv) >= 11)
   883			gen11_sseu_info_init(dev_priv);
   884	
   885		if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
   886			DRM_INFO("Disabling ppGTT for VT-d support\n");
   887			info->ppgtt = INTEL_PPGTT_NONE;
   888		}
   889	
   890		if (opt_config)
   891			dev_priv->opt_config = opt_config;
   892	
   893		/* Initialize command stream timestamp frequency */
   894		runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
   895	}
   896	

---
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