From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dmitry Osipenko Subject: [PATCH v10 5/7] ARM: tegra: Don't apply CPU erratas in insecure mode Date: Mon, 18 Mar 2019 01:52:08 +0300 Message-ID: <20190317225211.23091-6-digetx@gmail.com> References: <20190317225211.23091-1-digetx@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20190317225211.23091-1-digetx@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: Russell King , Thierry Reding , Jonathan Hunter , Robert Yang , =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Cc: linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-tegra@vger.kernel.org CPU isn't allowed to touch secure registers while running under secure monitor. Hence skip applying of CPU erratas in the reset handler if Trusted Foundations firmware presents. Partially based on work done by Michał Mirosław [1]. [1] https://www.spinics.net/lists/arm-kernel/msg594768.html Tested-by: Robert Yang Tested-by: Michał Mirosław Signed-off-by: Michał Mirosław Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/reset-handler.S | 23 ++++++++++++----------- arch/arm/mach-tegra/reset.c | 3 +++ arch/arm/mach-tegra/reset.h | 9 +++++++-- arch/arm/mach-tegra/sleep-tegra20.S | 4 ++++ 4 files changed, 26 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index e22ccf87eded..809fbc200cef 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -29,8 +29,6 @@ #define PMC_SCRATCH41 0x140 -#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) - #ifdef CONFIG_PM_SLEEP /* * tegra_resume @@ -121,6 +119,12 @@ ENTRY(__tegra_cpu_reset_handler) cpsid aif, 0x13 @ SVC mode, interrupts disabled tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 + + adr r12, __tegra_cpu_reset_handler_data + ldr r5, [r12, #RESET_DATA(TF_PRESENT)] + cmp r5, #0 + bne after_errata + #ifdef CONFIG_ARCH_TEGRA_2x_SOC t20_check: cmp r6, #TEGRA20 @@ -155,7 +159,6 @@ after_errata: and r10, r10, #0x3 @ R10 = CPU number mov r11, #1 mov r11, r11, lsl r10 @ R11 = CPU mask - adr r12, __tegra_cpu_reset_handler_data #ifdef CONFIG_SMP /* Does the OS know about this CPU? */ @@ -169,10 +172,9 @@ after_errata: cmp r6, #TEGRA20 bne 1f /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ - mov32 r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET mov r0, #CPU_NOT_RESETTABLE cmp r10, #0 - strbne r0, [r5, #__tegra20_cpu1_resettable_status_offset] + strbne r0, [r12, #RESET_DATA(RESETTABLE_STATUS)] 1: #endif @@ -277,14 +279,13 @@ ENDPROC(__tegra_cpu_reset_handler) .align L1_CACHE_SHIFT .type __tegra_cpu_reset_handler_data, %object .globl __tegra_cpu_reset_handler_data + .globl __tegra_cpu_reset_handler_data_offset + .equ __tegra_cpu_reset_handler_data_offset, \ + . - __tegra_cpu_reset_handler_start __tegra_cpu_reset_handler_data: - .rept TEGRA_RESET_DATA_SIZE - .long 0 + .rept TEGRA_RESET_DATA_SIZE + .long 0 .endr - .globl __tegra20_cpu1_resettable_status_offset - .equ __tegra20_cpu1_resettable_status_offset, \ - . - __tegra_cpu_reset_handler_start - .byte 0 .align L1_CACHE_SHIFT ENTRY(__tegra_cpu_reset_handler_end) diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index dc558892753c..b02ae7699842 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "iomap.h" #include "irammap.h" @@ -89,6 +90,8 @@ static void __init tegra_cpu_reset_handler_enable(void) void __init tegra_cpu_reset_handler_init(void) { + __tegra_cpu_reset_handler_data[TEGRA_RESET_TF_PRESENT] = + trusted_foundations_registered(); #ifdef CONFIG_SMP __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h index 9c479c7925b8..db0e6b3097ab 100644 --- a/arch/arm/mach-tegra/reset.h +++ b/arch/arm/mach-tegra/reset.h @@ -25,7 +25,11 @@ #define TEGRA_RESET_STARTUP_SECONDARY 3 #define TEGRA_RESET_STARTUP_LP2 4 #define TEGRA_RESET_STARTUP_LP1 5 -#define TEGRA_RESET_DATA_SIZE 6 +#define TEGRA_RESET_RESETTABLE_STATUS 6 +#define TEGRA_RESET_TF_PRESENT 7 +#define TEGRA_RESET_DATA_SIZE 8 + +#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) #ifndef __ASSEMBLY__ @@ -49,7 +53,8 @@ void __tegra_cpu_reset_handler_end(void); (u32)__tegra_cpu_reset_handler_start))) #define tegra20_cpu1_resettable_status \ (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ - (u32)__tegra20_cpu1_resettable_status_offset)) + ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \ + (u32)__tegra_cpu_reset_handler_start))) #endif #define tegra_cpu_reset_handler_offset \ diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index dedeebfccc55..50d51d3465f6 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -28,6 +28,7 @@ #include #include "irammap.h" +#include "reset.h" #include "sleep.h" #define EMC_CFG 0xc @@ -53,6 +54,9 @@ #define APB_MISC_XM2CFGCPADCTRL2 0x8e4 #define APB_MISC_XM2CFGDPADCTRL2 0x8e8 +#define __tegra20_cpu1_resettable_status_offset \ + (__tegra_cpu_reset_handler_data_offset + RESET_DATA(RESETTABLE_STATUS)) + .macro pll_enable, rd, r_car_base, pll_base ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 30) -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.7 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25931C43381 for ; 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cm0vbWFjaC10ZWdyYS9yZXNldC1oYW5kbGVyLlMgfCAyMyArKysrKysrKysrKystLS0tLS0tLS0t LQogYXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNldC5jICAgICAgICAgfCAgMyArKysKIGFyY2gvYXJt L21hY2gtdGVncmEvcmVzZXQuaCAgICAgICAgIHwgIDkgKysrKysrKy0tCiBhcmNoL2FybS9tYWNo LXRlZ3JhL3NsZWVwLXRlZ3JhMjAuUyB8ICA0ICsrKysKIDQgZmlsZXMgY2hhbmdlZCwgMjYgaW5z ZXJ0aW9ucygrKSwgMTMgZGVsZXRpb25zKC0pCgpkaWZmIC0tZ2l0IGEvYXJjaC9hcm0vbWFjaC10 ZWdyYS9yZXNldC1oYW5kbGVyLlMgYi9hcmNoL2FybS9tYWNoLXRlZ3JhL3Jlc2V0LWhhbmRsZXIu UwppbmRleCBlMjJjY2Y4N2VkZWQuLjgwOWZiYzIwMGNlZiAxMDA2NDQKLS0tIGEvYXJjaC9hcm0v bWFjaC10ZWdyYS9yZXNldC1oYW5kbGVyLlMKKysrIGIvYXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNl dC1oYW5kbGVyLlMKQEAgLTI5LDggKzI5LDYgQEAKIAogI2RlZmluZSBQTUNfU0NSQVRDSDQxCTB4 MTQwCiAKLSNkZWZpbmUgUkVTRVRfREFUQSh4KQkoKFRFR1JBX1JFU0VUXyMjeCkqNCkKLQogI2lm ZGVmIENPTkZJR19QTV9TTEVFUAogLyoKICAqCXRlZ3JhX3Jlc3VtZQpAQCAtMTIxLDYgKzExOSwx MiBAQCBFTlRSWShfX3RlZ3JhX2NwdV9yZXNldF9oYW5kbGVyKQogCWNwc2lkCWFpZiwgMHgxMwkJ CUAgU1ZDIG1vZGUsIGludGVycnVwdHMgZGlzYWJsZWQKIAogCXRlZ3JhX2dldF9zb2NfaWQgVEVH UkFfQVBCX01JU0NfQkFTRSwgcjYKKworCWFkcglyMTIsIF9fdGVncmFfY3B1X3Jlc2V0X2hhbmRs ZXJfZGF0YQorCWxkcglyNSwgW3IxMiwgI1JFU0VUX0RBVEEoVEZfUFJFU0VOVCldCisJY21wCXI1 LCAjMAorCWJuZQlhZnRlcl9lcnJhdGEKKwogI2lmZGVmIENPTkZJR19BUkNIX1RFR1JBXzJ4X1NP QwogdDIwX2NoZWNrOgogCWNtcAlyNiwgI1RFR1JBMjAKQEAgLTE1NSw3ICsxNTksNiBAQCBhZnRl cl9lcnJhdGE6CiAJYW5kCXIxMCwgcjEwLCAjMHgzCQkJQCBSMTAgPSBDUFUgbnVtYmVyCiAJbW92 CXIxMSwgIzEKIAltb3YJcjExLCByMTEsIGxzbCByMTAgIAkJQCBSMTEgPSBDUFUgbWFzawotCWFk cglyMTIsIF9fdGVncmFfY3B1X3Jlc2V0X2hhbmRsZXJfZGF0YQogCiAjaWZkZWYgQ09ORklHX1NN UAogCS8qIERvZXMgdGhlIE9TIGtub3cgYWJvdXQgdGhpcyBDUFU/ICovCkBAIC0xNjksMTAgKzE3 Miw5IEBAIGFmdGVyX2VycmF0YToKIAljbXAJcjYsICNURUdSQTIwCiAJYm5lCTFmCiAJLyogSWYg bm90IENQVTAsIGRvbid0IGxldCBDUFUwIHJlc2V0IENQVTEgbm93IHRoYXQgQ1BVMSBpcyBjb21p bmcgdXAuICovCi0JbW92MzIJcjUsIFRFR1JBX0lSQU1fQkFTRSArIFRFR1JBX0lSQU1fUkVTRVRf SEFORExFUl9PRkZTRVQKIAltb3YJcjAsICNDUFVfTk9UX1JFU0VUVEFCTEUKIAljbXAJcjEwLCAj MAotCXN0cmJuZQlyMCwgW3I1LCAjX190ZWdyYTIwX2NwdTFfcmVzZXR0YWJsZV9zdGF0dXNfb2Zm c2V0XQorCXN0cmJuZQlyMCwgW3IxMiwgI1JFU0VUX0RBVEEoUkVTRVRUQUJMRV9TVEFUVVMpXQog MToKICNlbmRpZgogCkBAIC0yNzcsMTQgKzI3OSwxMyBAQCBFTkRQUk9DKF9fdGVncmFfY3B1X3Jl c2V0X2hhbmRsZXIpCiAJLmFsaWduIEwxX0NBQ0hFX1NISUZUCiAJLnR5cGUJX190ZWdyYV9jcHVf cmVzZXRfaGFuZGxlcl9kYXRhLCAlb2JqZWN0CiAJLmdsb2JsCV9fdGVncmFfY3B1X3Jlc2V0X2hh bmRsZXJfZGF0YQorCS5nbG9ibAlfX3RlZ3JhX2NwdV9yZXNldF9oYW5kbGVyX2RhdGFfb2Zmc2V0 CisJLmVxdQlfX3RlZ3JhX2NwdV9yZXNldF9oYW5kbGVyX2RhdGFfb2Zmc2V0LCBcCisJCQkJCS4g LSBfX3RlZ3JhX2NwdV9yZXNldF9oYW5kbGVyX3N0YXJ0CiBfX3RlZ3JhX2NwdV9yZXNldF9oYW5k bGVyX2RhdGE6Ci0JLnJlcHQJVEVHUkFfUkVTRVRfREFUQV9TSVpFCi0JLmxvbmcJMAorCS5yZXB0 ICAgVEVHUkFfUkVTRVRfREFUQV9TSVpFCisJLmxvbmcgICAwCiAJLmVuZHIKLQkuZ2xvYmwJX190 ZWdyYTIwX2NwdTFfcmVzZXR0YWJsZV9zdGF0dXNfb2Zmc2V0Ci0JLmVxdQlfX3RlZ3JhMjBfY3B1 MV9yZXNldHRhYmxlX3N0YXR1c19vZmZzZXQsIFwKLQkJCQkJLiAtIF9fdGVncmFfY3B1X3Jlc2V0 X2hhbmRsZXJfc3RhcnQKLQkuYnl0ZQkwCiAJLmFsaWduIEwxX0NBQ0hFX1NISUZUCiAKIEVOVFJZ KF9fdGVncmFfY3B1X3Jlc2V0X2hhbmRsZXJfZW5kKQpkaWZmIC0tZ2l0IGEvYXJjaC9hcm0vbWFj aC10ZWdyYS9yZXNldC5jIGIvYXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNldC5jCmluZGV4IGRjNTU4 ODkyNzUzYy4uYjAyYWU3Njk5ODQyIDEwMDY0NAotLS0gYS9hcmNoL2FybS9tYWNoLXRlZ3JhL3Jl c2V0LmMKKysrIGIvYXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNldC5jCkBAIC0yNCw2ICsyNCw3IEBA CiAjaW5jbHVkZSA8YXNtL2NhY2hlZmx1c2guaD4KICNpbmNsdWRlIDxhc20vZmlybXdhcmUuaD4K ICNpbmNsdWRlIDxhc20vaGFyZHdhcmUvY2FjaGUtbDJ4MC5oPgorI2luY2x1ZGUgPGFzbS90cnVz dGVkX2ZvdW5kYXRpb25zLmg+CiAKICNpbmNsdWRlICJpb21hcC5oIgogI2luY2x1ZGUgImlyYW1t YXAuaCIKQEAgLTg5LDYgKzkwLDggQEAgc3RhdGljIHZvaWQgX19pbml0IHRlZ3JhX2NwdV9yZXNl dF9oYW5kbGVyX2VuYWJsZSh2b2lkKQogCiB2b2lkIF9faW5pdCB0ZWdyYV9jcHVfcmVzZXRfaGFu ZGxlcl9pbml0KHZvaWQpCiB7CisJX190ZWdyYV9jcHVfcmVzZXRfaGFuZGxlcl9kYXRhW1RFR1JB X1JFU0VUX1RGX1BSRVNFTlRdID0KKwkJdHJ1c3RlZF9mb3VuZGF0aW9uc19yZWdpc3RlcmVkKCk7 CiAKICNpZmRlZiBDT05GSUdfU01QCiAJX190ZWdyYV9jcHVfcmVzZXRfaGFuZGxlcl9kYXRhW1RF R1JBX1JFU0VUX01BU0tfUFJFU0VOVF0gPQpkaWZmIC0tZ2l0IGEvYXJjaC9hcm0vbWFjaC10ZWdy YS9yZXNldC5oIGIvYXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNldC5oCmluZGV4IDljNDc5Yzc5MjVi OC4uZGIwZTZiMzA5N2FiIDEwMDY0NAotLS0gYS9hcmNoL2FybS9tYWNoLXRlZ3JhL3Jlc2V0LmgK KysrIGIvYXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNldC5oCkBAIC0yNSw3ICsyNSwxMSBAQAogI2Rl ZmluZSBURUdSQV9SRVNFVF9TVEFSVFVQX1NFQ09OREFSWQkzCiAjZGVmaW5lIFRFR1JBX1JFU0VU X1NUQVJUVVBfTFAyCQk0CiAjZGVmaW5lIFRFR1JBX1JFU0VUX1NUQVJUVVBfTFAxCQk1Ci0jZGVm aW5lIFRFR1JBX1JFU0VUX0RBVEFfU0laRQkJNgorI2RlZmluZSBURUdSQV9SRVNFVF9SRVNFVFRB QkxFX1NUQVRVUwk2CisjZGVmaW5lIFRFR1JBX1JFU0VUX1RGX1BSRVNFTlQJCTcKKyNkZWZpbmUg VEVHUkFfUkVTRVRfREFUQV9TSVpFCQk4CisKKyNkZWZpbmUgUkVTRVRfREFUQSh4KQkoKFRFR1JB X1JFU0VUXyMjeCkqNCkKIAogI2lmbmRlZiBfX0FTU0VNQkxZX18KIApAQCAtNDksNyArNTMsOCBA QCB2b2lkIF9fdGVncmFfY3B1X3Jlc2V0X2hhbmRsZXJfZW5kKHZvaWQpOwogCSAodTMyKV9fdGVn cmFfY3B1X3Jlc2V0X2hhbmRsZXJfc3RhcnQpKSkKICNkZWZpbmUgdGVncmEyMF9jcHUxX3Jlc2V0 dGFibGVfc3RhdHVzIFwKIAkoSU9fQUREUkVTUyhURUdSQV9JUkFNX0JBU0UgKyBURUdSQV9JUkFN X1JFU0VUX0hBTkRMRVJfT0ZGU0VUICsgXAotCSAodTMyKV9fdGVncmEyMF9jcHUxX3Jlc2V0dGFi bGVfc3RhdHVzX29mZnNldCkpCisJKCh1MzIpJl9fdGVncmFfY3B1X3Jlc2V0X2hhbmRsZXJfZGF0 YVtURUdSQV9SRVNFVF9SRVNFVFRBQkxFX1NUQVRVU10gLSBcCisJICh1MzIpX190ZWdyYV9jcHVf cmVzZXRfaGFuZGxlcl9zdGFydCkpKQogI2VuZGlmCiAKICNkZWZpbmUgdGVncmFfY3B1X3Jlc2V0 X2hhbmRsZXJfb2Zmc2V0IFwKZGlmZiAtLWdpdCBhL2FyY2gvYXJtL21hY2gtdGVncmEvc2xlZXAt dGVncmEyMC5TIGIvYXJjaC9hcm0vbWFjaC10ZWdyYS9zbGVlcC10ZWdyYTIwLlMKaW5kZXggZGVk ZWViZmNjYzU1Li41MGQ1MWQzNDY1ZjYgMTAwNjQ0Ci0tLSBhL2FyY2gvYXJtL21hY2gtdGVncmEv c2xlZXAtdGVncmEyMC5TCisrKyBiL2FyY2gvYXJtL21hY2gtdGVncmEvc2xlZXAtdGVncmEyMC5T CkBAIC0yOCw2ICsyOCw3IEBACiAjaW5jbHVkZSA8YXNtL2NhY2hlLmg+CiAKICNpbmNsdWRlICJp cmFtbWFwLmgiCisjaW5jbHVkZSAicmVzZXQuaCIKICNpbmNsdWRlICJzbGVlcC5oIgogCiAjZGVm aW5lIEVNQ19DRkcJCQkJMHhjCkBAIC01Myw2ICs1NCw5IEBACiAjZGVmaW5lIEFQQl9NSVNDX1hN MkNGR0NQQURDVFJMMgkweDhlNAogI2RlZmluZSBBUEJfTUlTQ19YTTJDRkdEUEFEQ1RSTDIJMHg4 ZTgKIAorI2RlZmluZSBfX3RlZ3JhMjBfY3B1MV9yZXNldHRhYmxlX3N0YXR1c19vZmZzZXQgXAor CShfX3RlZ3JhX2NwdV9yZXNldF9oYW5kbGVyX2RhdGFfb2Zmc2V0ICsgUkVTRVRfREFUQShSRVNF VFRBQkxFX1NUQVRVUykpCisKIC5tYWNybyBwbGxfZW5hYmxlLCByZCwgcl9jYXJfYmFzZSwgcGxs X2Jhc2UKIAlsZHIJXHJkLCBbXHJfY2FyX2Jhc2UsICNccGxsX2Jhc2VdCiAJdHN0CVxyZCwgIygx IDw8IDMwKQotLSAKMi4yMC4xCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5l bEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4v bGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=