Re: [PATCH] ARM: imx6: cpuidle: omit the unnecessary unmask of GINT

From: Shawn Guo <shawnguo@kernel.org>
To: Peng Fan <peng.fan@nxp.com>
Cc: "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
	Kohji Okuno <okuno.kohji@jp.panasonic.com>,
	dl-linux-imx <linux-imx@nxp.com>,
	"kernel@pengutronix.de" <kernel@pengutronix.de>,
	"festevam@gmail.com" <festevam@gmail.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] ARM: imx6: cpuidle: omit the unnecessary unmask of GINT
Date: Wed, 20 Mar 2019 22:28:52 +0800	[thread overview]
Message-ID: <20190320142850.GA8337@dragon> (raw)
In-Reply-To: <AM0PR04MB44814FA6081FE4295667ED4888410@AM0PR04MB4481.eurprd04.prod.outlook.com>

Hi Peng,

On Wed, Mar 20, 2019 at 07:59:19AM +0000, Peng Fan wrote:
> > So are you saying the workaround of ERR007265 does not need to apply on
> > WAIT_CLOCKED mode?  But WAIT_CLOCKED is one of low-power modes,
> > isn't it?
> 
> If understand correct, I think WAIT_CLOCKED is for run mode, not wait/stop mode.
> 
> According to i.MX6Q RM, "18.6.18 CCM Low Power Control Register (CCM_CLPCR)"
> 
> Setting the low power mode that system will enter on next assertion of dsm_request signal.
> NOTE: Set CCM_CGPR[INT_MEM_CLK_LPM] and CCM_CGPR[1] bits to 1 when setting
> CCM_CLPCR[LPM] bits to 01 (WAIT Mode) or 10 (STOP mode) without power gating.
> CCM_CGPR[INT_MEM_CLK_LPM] and CCM_CGPR[1] bits do not have to be set for STOP
> mode entry.
> 00 Remain in run mode
> 01 Transfer to wait mode
> 10 Transfer to stop mode
> 11 Reserved
> 
> And according to the function:
> int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
> {
>         u32 val = readl_relaxed(ccm_base + CLPCR);
> 
>         val &= ~BM_CLPCR_LPM;
>         switch (mode) {
>         case WAIT_CLOCKED:
>                 break;
> 
> WAIT_CLOCKED will clear the LPM bits.
> 
> 
> According to https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
> "
> ERR007265 CCM: When improper low-power sequence is used, the SoC enters
> low power mode before the ARM core executes WFI
> 
> When software tries to enter Low-Power mode with the following sequence, the SoC enters
> Low-Power mode before the ARM core executes the WFI instruction:
> 1. Set CCM_CLPCR[1:0] to 2’b00
> 2. ARM core enters WFI
> 3. ARM core wakeup from an interrupt event, which is masked by GPC or not visible to GPC,
> such as an interrupt from a local timer
> 4. Set CCM_CLPCR[1:0] to 2’b01 or 2’b10
> 5. ARM core executes WFI
> Before the last step, the SoC enters WAIT mode if CCM_CLPCR[1:0] is set to 2’b01, or STOP
> mode if CCM_CLPCR[1:0] is set to 2’b10.
> "
> 
> It mentions that soc will enter wait/stop mode early before wfi if set CCM_CLPCR to 1/2.
> But WAIT_CLOCKED is not wait mode or stop mode, it will set LPM to run mode.

Thanks much for the detailed explanation.  I messed WAIT_CLOCKED with
WAIT_UNCLOCKED.  Yes, I agree it's an optimization that we skip applying
the workaround to WAIT_CLOCKED.

Shawn

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