From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E179C43381 for ; Fri, 22 Mar 2019 12:14:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F26BB218A1 for ; Fri, 22 Mar 2019 12:14:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1553256893; bh=ptuR0qwy7TTx++QePk0sHPicn9akMSZYEMm46HXuxXQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=Nv0J4Qx0DyH/EVM+Bw271OsgZNAO6nsP7vx1uzT7zXYmLc3J/Og/B4L67vAIF/Eng nDEYZEnyC+YOWWvbgGSCa+lJmNfvBllGvn6eIvRvb98ci6UMydFDcm8D1JJYAtUN3q zhH3aRiqFsQ7CQcX1GEKBL+1wDZhBJ20XfwIGvXw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389982AbfCVMOv (ORCPT ); Fri, 22 Mar 2019 08:14:51 -0400 Received: from mail.kernel.org ([198.145.29.99]:53026 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389465AbfCVMOq (ORCPT ); Fri, 22 Mar 2019 08:14:46 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E5B692083D; Fri, 22 Mar 2019 12:14:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1553256885; bh=ptuR0qwy7TTx++QePk0sHPicn9akMSZYEMm46HXuxXQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eZxqRa/tas4DIn22iDlvjdqMLGZVl+pl7uRq0Wwgf4BQUoU89E8aX57qqIrM6A15T c56p3cdR7OZnd6ZJWcWj7bBFJeQGs4c2V3bH+wyPL/pgUUBsTnnrtGSZ3NBqaGstb6 D71gewSJP2qBe656KzN+weL6ni3lqOtZ5q3w5Izg= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, David Lechner , Vignesh R , Mark Brown Subject: [PATCH 5.0 067/238] spi: omap2-mcspi: Fix DMA and FIFO event trigger size mismatch Date: Fri, 22 Mar 2019 12:14:46 +0100 Message-Id: <20190322111302.566400072@linuxfoundation.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190322111258.383569278@linuxfoundation.org> References: <20190322111258.383569278@linuxfoundation.org> User-Agent: quilt/0.65 X-stable: review X-Patchwork-Hint: ignore MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 5.0-stable review patch. If anyone has any objections, please let me know. ------------------ From: Vignesh R commit baf8b9f8d260c55a86405f70a384c29cda888476 upstream. Commit b682cffa3ac6 ("spi: omap2-mcspi: Set FIFO DMA trigger level to word length") broke SPI transfers where bits_per_word != 8. This is because of mimsatch between McSPI FIFO level event trigger size (SPI word length) and DMA request size(word length * maxburst). This leads to data corruption, lockup and errors like: spi1.0: EOW timed out Fix this by setting DMA maxburst size to 1 so that McSPI FIFO level event trigger size matches DMA request size. Fixes: b682cffa3ac6 ("spi: omap2-mcspi: Set FIFO DMA trigger level to word length") Cc: stable@vger.kernel.org Reported-by: David Lechner Tested-by: David Lechner Signed-off-by: Vignesh R Signed-off-by: Mark Brown Signed-off-by: Greg Kroah-Hartman --- drivers/spi/spi-omap2-mcspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/drivers/spi/spi-omap2-mcspi.c +++ b/drivers/spi/spi-omap2-mcspi.c @@ -623,8 +623,8 @@ omap2_mcspi_txrx_dma(struct spi_device * cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; cfg.src_addr_width = width; cfg.dst_addr_width = width; - cfg.src_maxburst = es; - cfg.dst_maxburst = es; + cfg.src_maxburst = 1; + cfg.dst_maxburst = 1; rx = xfer->rx_buf; tx = xfer->tx_buf;