[PATCH V3 00/23] perf: Add Icelake support

[kan.liang@linux.intel.com]

From: Kan Liang <kan.liang@linux.intel.com>

The patch series intends to add Icelake support for Linux perf.

PATCH 1-18: Kernel patches to support Icelake.
 - 1-5: Support adaptive PEBS feature
 - 6-7: Enable core support with some new features, e.g. 8 generic
   counters, new event constraints, a new fixed counter.
 - 8-11: Enable cstate, rapl, msr and uncore support on Icelake
 - 12-18: Support hardware Metrics counters and SLOT fixed counter for
   Topdown events.
 - 19: Support CPUID 10.ECX to disable fixed counters

PATCH 20-23: Perf tool patches to support XMM, Topdown and event list.

Changes since V2:
- Make the setup_pebs_sample_data() a function pointer argument
- Use cpuc->pebs_record_size unconditionally
- Add comments for EVENT_CONSTRAINT_RANGE
- Correct the Author of "perf/x86: Support constraint ranges"

Changes since V1:
- Avoid the interface changes for perf_reg_value() and
  perf_output_sample_regs().
- Remove the extra_regs in struct perf_sample_data.
- Add struct x86_perf_regs
- Add has_xmm_regs to indicate the specific platform which support XMM
  registers collection.
- Add check in x86_pmu_hw_config() to reject invalid config of regs_user
  and regs_intr.
- Rename intel_hsw_weight and intel_hsw_transaction
- Add missed inline for intel_get_tsx_transaction()
- Add new patch to extract code of event update in short period
- Code rebase on top of c634dc6bdede
- Rename @d to pebs_data_cfg
- Make pebs_update_adaptive_cfg readable
- Clear pebs_data_cfg and pebs_record_size for first PEBS in add
- Don't clear ICL_EVENTSEL_ADAPTIVE. Rely on MSR_PEBS_CFG settings
- Change PEBS record parsing order (bug fix)
- Support struct x86_perf_regs
- make get_pebs_status generic
- specific intel_pmu_drain_pebs_icl()
- Use cpuc->pebs_record_size to replace format_size
- Use 'size' to replace 'range_end' for constraint ranges
- Add x86_pmu.has_xmm_regs = true;
- Add more explanation in change log of REMOVE transaction
- Make perf_regs.h consistent between kernel and user space

Andi Kleen (11):
  perf/x86/intel: Extract memory code PEBS parser for reuse
  perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them
  perf/core: Support a REMOVE transaction
  perf/x86/intel: Basic support for metrics counters
  perf/x86/intel: Support overflows on SLOTS
  perf/x86/intel: Set correct weight for topdown subevent counters
  perf/x86/intel: Export new top down events for Icelake
  perf/x86/intel: Support CPUID 10.ECX to disable fixed counters
  perf, tools: Add support for recording and printing XMM registers
  perf, tools, stat: Support new per thread TopDown metrics
  perf, tools: Add documentation for topdown metrics

Kan Liang (11):
  perf/x86: Support outputting XMM registers
  perf/x86/intel/ds: Extract code of event update in short period
  perf/x86/intel: Support adaptive PEBSv4
  perf/x86/intel: Add Icelake support
  perf/x86/intel/cstate: Add Icelake support
  perf/x86/intel/rapl: Add Icelake support
  perf/x86/msr: Add Icelake support
  perf/x86/intel/uncore: Add Intel Icelake uncore support
  perf/x86/intel: Support hardware TopDown metrics
  perf/x86/intel: Disable sampling read slots and topdown
  perf vendor events intel: Add JSON files for Icelake

Peter Zijlstra (1):
  perf/x86: Support constraint ranges

 arch/x86/events/core.c                        |  81 +-
 arch/x86/events/intel/core.c                  | 422 ++++++++-
 arch/x86/events/intel/cstate.c                |   2 +
 arch/x86/events/intel/ds.c                    | 496 ++++++++--
 arch/x86/events/intel/lbr.c                   |  35 +-
 arch/x86/events/intel/rapl.c                  |   2 +
 arch/x86/events/intel/uncore.c                |   6 +
 arch/x86/events/intel/uncore.h                |   1 +
 arch/x86/events/intel/uncore_snb.c            |  91 ++
 arch/x86/events/msr.c                         |   1 +
 arch/x86/events/perf_event.h                  |  93 +-
 arch/x86/include/asm/intel_ds.h               |   2 +-
 arch/x86/include/asm/msr-index.h              |   4 +
 arch/x86/include/asm/perf_event.h             |  79 +-
 arch/x86/include/uapi/asm/perf_regs.h         |  26 +-
 arch/x86/kernel/perf_regs.c                   |  18 +-
 include/linux/perf_event.h                    |   7 +
 kernel/events/core.c                          |   5 +
 tools/arch/x86/include/uapi/asm/perf_regs.h   |  26 +-
 tools/perf/Documentation/perf-stat.txt        |   9 +-
 tools/perf/Documentation/topdown.txt          | 223 +++++
 tools/perf/arch/x86/include/perf_regs.h       |  29 +-
 tools/perf/arch/x86/util/perf_regs.c          |  16 +
 tools/perf/builtin-stat.c                     |  24 +
 .../pmu-events/arch/x86/icelake/cache.json    | 552 +++++++++++
 .../arch/x86/icelake/floating-point.json      |  90 ++
 .../pmu-events/arch/x86/icelake/frontend.json | 424 +++++++++
 .../pmu-events/arch/x86/icelake/memory.json   | 410 ++++++++
 .../pmu-events/arch/x86/icelake/other.json    | 133 +++
 .../pmu-events/arch/x86/icelake/pipeline.json | 892 ++++++++++++++++++
 .../arch/x86/icelake/virtual-memory.json      | 236 +++++
 tools/perf/pmu-events/arch/x86/mapfile.csv    |   1 +
 tools/perf/util/perf_regs.h                   |   1 +
 tools/perf/util/stat-shadow.c                 |  89 ++
 tools/perf/util/stat.c                        |   4 +
 tools/perf/util/stat.h                        |   8 +
 36 files changed, 4418 insertions(+), 120 deletions(-)
 create mode 100644 tools/perf/Documentation/topdown.txt
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/cache.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/floating-point.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/frontend.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/memory.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/other.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json

-- 
2.17.1