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From: kan.liang@linux.intel.com
To: peterz@infradead.org, acme@kernel.org, mingo@redhat.com,
	linux-kernel@vger.kernel.org
Cc: tglx@linutronix.de, jolsa@kernel.org, eranian@google.com,
	alexander.shishkin@linux.intel.com, ak@linux.intel.com,
	Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V3 08/23] perf/x86/intel/cstate: Add Icelake support
Date: Fri, 22 Mar 2019 09:37:03 -0700	[thread overview]
Message-ID: <20190322163718.2191-9-kan.liang@linux.intel.com> (raw)
In-Reply-To: <20190322163718.2191-1-kan.liang@linux.intel.com>

From: Kan Liang <kan.liang@linux.intel.com>

Icelake uses the same C-state residency events as Sandy Bridge.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---

No changes since V2.

 arch/x86/events/intel/cstate.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 94a4b7fc75d0..dd5658ec31d5 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -578,6 +578,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_X, glm_cstates),
 
 	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
+
+	X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_MOBILE, snb_cstates),
 	{ },
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
-- 
2.17.1


  parent reply	other threads:[~2019-03-22 16:40 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-22 16:36 [PATCH V3 00/23] perf: Add Icelake support kan.liang
2019-03-22 16:36 ` [PATCH V3 01/23] perf/x86: Support outputting XMM registers kan.liang
2019-03-22 17:08   ` Peter Zijlstra
2019-03-22 17:22     ` Andi Kleen
2019-03-23  9:56       ` Peter Zijlstra
2019-03-25 20:35         ` Liang, Kan
2019-03-26  0:02           ` Thomas Gleixner
2019-03-26  0:11   ` Thomas Gleixner
2019-03-26 13:14     ` Liang, Kan
2019-03-26 13:47       ` Thomas Gleixner
2019-03-26 13:55         ` Liang, Kan
2019-03-22 16:36 ` [PATCH V3 02/23] perf/x86/intel: Extract memory code PEBS parser for reuse kan.liang
2019-03-22 16:36 ` [PATCH V3 03/23] perf/x86/intel/ds: Extract code of event update in short period kan.liang
2019-03-22 16:36 ` [PATCH V3 04/23] perf/x86/intel: Support adaptive PEBSv4 kan.liang
2019-03-22 16:37 ` [PATCH V3 05/23] perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them kan.liang
2019-03-22 16:37 ` [PATCH V3 06/23] perf/x86: Support constraint ranges kan.liang
2019-03-22 16:37 ` [PATCH V3 07/23] perf/x86/intel: Add Icelake support kan.liang
2019-03-22 16:37 ` kan.liang [this message]
2019-03-22 16:37 ` [PATCH V3 09/23] perf/x86/intel/rapl: " kan.liang
2019-03-22 16:37 ` [PATCH V3 10/23] perf/x86/msr: " kan.liang
2019-03-22 16:37 ` [PATCH V3 11/23] perf/x86/intel/uncore: Add Intel Icelake uncore support kan.liang
2019-03-22 16:37 ` [PATCH V3 12/23] perf/core: Support a REMOVE transaction kan.liang
2019-03-22 16:37 ` [PATCH V3 13/23] perf/x86/intel: Basic support for metrics counters kan.liang
2019-03-22 16:37 ` [PATCH V3 14/23] perf/x86/intel: Support overflows on SLOTS kan.liang
2019-03-22 16:37 ` [PATCH V3 15/23] perf/x86/intel: Support hardware TopDown metrics kan.liang
2019-03-22 16:37 ` [PATCH V3 16/23] perf/x86/intel: Set correct weight for topdown subevent counters kan.liang
2019-03-22 16:37 ` [PATCH V3 17/23] perf/x86/intel: Export new top down events for Icelake kan.liang
2019-03-22 16:37 ` [PATCH V3 18/23] perf/x86/intel: Disable sampling read slots and topdown kan.liang
2019-03-22 16:37 ` [PATCH V3 19/23] perf/x86/intel: Support CPUID 10.ECX to disable fixed counters kan.liang
2019-03-22 16:37 ` [PATCH V3 20/23] perf, tools: Add support for recording and printing XMM registers kan.liang
2019-03-22 16:37 ` [PATCH 21/23] perf, tools, stat: Support new per thread TopDown metrics kan.liang
2019-03-22 16:37 ` [PATCH V3 22/23] perf, tools: Add documentation for topdown metrics kan.liang
2019-03-22 16:37 ` [PATCH V3 23/23] perf vendor events intel: Add JSON files for Icelake kan.liang

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