From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAD83C43381 for ; Mon, 25 Mar 2019 11:22:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9768E20863 for ; Mon, 25 Mar 2019 11:22:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730930AbfCYLWL (ORCPT ); Mon, 25 Mar 2019 07:22:11 -0400 Received: from mga04.intel.com ([192.55.52.120]:63575 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730472AbfCYLWL (ORCPT ); Mon, 25 Mar 2019 07:22:11 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Mar 2019 04:22:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,256,1549958400"; d="scan'208";a="137209955" Received: from lahna.fi.intel.com (HELO lahna) ([10.237.72.157]) by fmsmga007.fm.intel.com with SMTP; 25 Mar 2019 04:22:07 -0700 Received: by lahna (sSMTP sendmail emulation); Mon, 25 Mar 2019 13:22:06 +0200 Date: Mon, 25 Mar 2019 13:22:06 +0200 From: Mika Westerberg To: Lukas Wunner Cc: linux-kernel@vger.kernel.org, Michael Jamet , Yehezkel Bernat , Andreas Noever , "David S . Miller" , Andy Shevchenko , netdev@vger.kernel.org Subject: Re: [PATCH v2 17/28] thunderbolt: Add support for full PCIe daisy chains Message-ID: <20190325112206.GH3622@lahna.fi.intel.com> References: <20190206131738.43696-1-mika.westerberg@linux.intel.com> <20190206131738.43696-18-mika.westerberg@linux.intel.com> <20190324113144.wubme46hby7rj6r2@wunner.de> <20190325095733.GC3622@lahna.fi.intel.com> <20190325111616.gjfkos666gz3blj2@wunner.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190325111616.gjfkos666gz3blj2@wunner.de> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.11.3 (2019-02-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 25, 2019 at 12:16:16PM +0100, Lukas Wunner wrote: > Yes, but my point is that it doesn't make much sense to establish a tunnel > between a switch and one of its parent switches unless that parent switch > is reachable from the root switch over a PCI tunnel or a series of PCI > tunnels. > > It may be worth checking that condition, or, if new tunnels are established > top-down in the daisy-chain and tunnel establishment has failed for a > switch, to not establish tunnels for switches beyond that one. OK, got it :)