From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller From: Rob Herring Message-Id: <20190328131657.GA9056@bogus> Date: Thu, 28 Mar 2019 08:16:57 -0500 To: Yash Shah Cc: linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, palmer@sifive.com, paul.walmsley@sifive.com, linux-kernel@vger.kernel.org, mark.rutland@arm.com, aou@eecs.berkeley.edu, bp@alien8.de, mchehab@kernel.org, devicetree@vger.kernel.org List-ID: T24gVHVlLCBNYXIgMTIsIDIwMTkgYXQgMDI6NTE6MDBQTSArMDUzMCwgWWFzaCBTaGFoIHdyb3Rl Ogo+IERUIGRvY3VtZW50YXRpb24gZm9yIEwyIGNhY2hlIGNvbnRyb2xsZXIgYWRkZWQuCj4gCj4g U2lnbmVkLW9mZi1ieTogWWFzaCBTaGFoIDx5YXNoLnNoYWhAc2lmaXZlLmNvbT4KPiAtLS0KPiAg Li4uL2RldmljZXRyZWUvYmluZGluZ3MvZWRhYy9zaWZpdmUtZWRhYy1sMi50eHQgICAgfCAzMSAr KysrKysrKysrKysrKysrKysrKysrCj4gIDEgZmlsZSBjaGFuZ2VkLCAzMSBpbnNlcnRpb25zKCsp Cj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3Mv ZWRhYy9zaWZpdmUtZWRhYy1sMi50eHQKPiAKPiBkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9k ZXZpY2V0cmVlL2JpbmRpbmdzL2VkYWMvc2lmaXZlLWVkYWMtbDIudHh0IGIvRG9jdW1lbnRhdGlv bi9kZXZpY2V0cmVlL2JpbmRpbmdzL2VkYWMvc2lmaXZlLWVkYWMtbDIudHh0Cj4gbmV3IGZpbGUg bW9kZSAxMDA2NDQKPiBpbmRleCAwMDAwMDAwLi5hYmNlMDlmCj4gLS0tIC9kZXYvbnVsbAo+ICsr KyBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9lZGFjL3NpZml2ZS1lZGFjLWwy LnR4dAo+IEBAIC0wLDAgKzEsMzEgQEAKPiArU2lGaXZlIEwyIENhY2hlIEVEQUMgZHJpdmVyIGRl dmljZSB0cmVlIGJpbmRpbmdzCj4gKy0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0KPiArVGhpcyBkcml2ZXIgdXNlcyB0aGUgRURBQyBmcmFtZXdvcmsgdG8g cmVwb3J0IEwyIGNhY2hlIGNvbnRyb2xsZXIgRUNDIGVycm9ycy4KCkJpbmRpbmdzIGFyZSBmb3Ig aC93IGJsb2Nrcywgbm90IGRyaXZlcnMuIChBbmQgQm9yaXMgbWF5IHdhbnQgYSBzaW5nbGUgCmRy aXZlciwgYnV0IGJpbmRpbmdzIHNob3VsZCByZWZsZWN0IHRoZSBoL3csIG5vdCB3aGF0IExpbnV4 IChjdXJyZW50bHkpIAp3YW50cy4KCkFyZSB0aGUgb25seSBjb250cm9scyBmb3IgRUNDPyBBcmUg YWxsIHRoZSBjYWNoZSBhdHRyaWJ1dGVzIGRpc2NvdmVyYWJsZSAKKHNpemUsIHdheXMsIGxpbmUg c2l6ZSwgbGV2ZWwsIGV0Yy4pPyAKCj4gKwo+ICstIGNvbXBhdGlibGU6IFNob3VsZCBiZSAic2lm aXZlLDxjaGlwPi1jY2FjaGUiIGFuZCAic2lmaXZlLGNjYWNoZTx2ZXJzaW9uPiIuCj4gKyAgU3Vw cG9ydGVkIGNvbXBhdGlibGUgc3RyaW5ncyBhcmU6Cj4gKyAgInNpZml2ZSxmdTU0MC1jMDAwLWNj YWNoZSIgZm9yIHRoZSBTaUZpdmUgY2FjaGUgY29udHJvbGxlciB2MCBhcyBpbnRlZ3JhdGVkCj4g KyAgb250byB0aGUgU2lGaXZlIEZVNTQwIGNoaXAsIGFuZCAic2lmaXZlLGNjYWNoZTAiIGZvciB0 aGUgU2lGaXZlCj4gKyAgY2FjaGUgY29udHJvbGxlciB2MCBJUCBibG9jayB3aXRoIG5vIGNoaXAg aW50ZWdyYXRpb24gdHdlYWtzLgo+ICsgIFBsZWFzZSByZWZlciB0byBzaWZpdmUtYmxvY2tzLWlw LXZlcnNpb25pbmcudHh0IGZvciBkZXRhaWxzCj4gKwo+ICstIGludGVycnVwdHM6IE11c3QgY29u dGFpbiAzIGVudHJpZXMgZm9yIEZVNTQwIChEaXJFcnJvciwgRGF0YUVycm9yLCBhbmQKPiArICBE YXRhRmFpbCBzaWduYWxzKSBvciA0IGVudHJpZXMgZm9yIG90aGVyIGNoaXBzIChEaXJFcnJvciwg RGlyRmFpbCwgRGF0YUVycm9yLAo+ICsgIGFuZCBEYXRhRmFpbCBzaWduYWxzKQoKMyBvciA0LCBi dXQgeW91IG9ubHkgaGF2ZSAxIGNoaXAgY29tcGF0aWJsZSBkZWZpbmVkPwoKPiArCj4gKy0gaW50 ZXJydXB0LXBhcmVudDogTXVzdCBiZSBjb3JlIGludGVycnVwdCBjb250cm9sbGVyCgpUaGlzIGlz IGltcGxpZWQgYW5kIGNvdWxkIGJlIGluIGEgcGFyZW50IG5vZGUuCgo+ICsKPiArLSByZWc6IFBo eXNpY2FsIGJhc2UgYWRkcmVzcyBhbmQgc2l6ZSBvZiBMMiBjYWNoZSBjb250cm9sbGVyIHJlZ2lz dGVycyBtYXAKPiArICBBIHNlY29uZCByYW5nZSBjYW4gaW5kaWNhdGUgTDIgTG9vc2VseSBJbnRl Z3JhdGVkIE1lbW9yeQo+ICsKPiArLSByZWctbmFtZXM6IE5hbWVzIGZvciB0aGUgY2VsbHMgb2Yg cmVnLCBtdXN0IGNvbnRhaW4gImNvbnRyb2wiIGFuZCAic2lkZWJhbmQiCj4gKwo+ICtFeGFtcGxl Ogo+ICsKPiArY2FjaGUtY29udHJvbGxlckAyMDEwMDAwIHsKPiArCWNvbXBhdGlibGUgPSAic2lm aXZlLGZ1NTQwLWMwMDAtY2NhY2hlIiwgInNpZml2ZSxjY2FjaGUwIjsKPiArCWludGVycnVwdC1w YXJlbnQgPSA8JnBsaWM+Owo+ICsJaW50ZXJydXB0cyA9IDwxIDIgMz47Cj4gKwlyZWcgPSA8MHgw IDB4MjAxMDAwMCAweDAgMHgxMDAwIDB4MCAweDgwMDAwMDAgMHgwIDB4MjAwMDAwMD47Cj4gKwly ZWctbmFtZXMgPSAiY29udHJvbCIsICJzaWRlYmFuZCI7Cj4gK307Cj4gLS0gCj4gMS45LjEKPgo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS, URIBL_BLOCKED,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5D3CC43381 for ; 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Thu, 28 Mar 2019 06:16:57 -0700 (PDT) Date: Thu, 28 Mar 2019 08:16:57 -0500 From: Rob Herring To: Yash Shah Subject: Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller Message-ID: <20190328131657.GA9056@bogus> References: <1552382461-13051-1-git-send-email-yash.shah@sifive.com> <1552382461-13051-2-git-send-email-yash.shah@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1552382461-13051-2-git-send-email-yash.shah@sifive.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190328_061700_259940_8BB7BCAF X-CRM114-Status: GOOD ( 16.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, aou@eecs.berkeley.edu, palmer@sifive.com, linux-kernel@vger.kernel.org, bp@alien8.de, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, mchehab@kernel.org, linux-edac@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Mar 12, 2019 at 02:51:00PM +0530, Yash Shah wrote: > DT documentation for L2 cache controller added. > > Signed-off-by: Yash Shah > --- > .../devicetree/bindings/edac/sifive-edac-l2.txt | 31 ++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > create mode 100644 Documentation/devicetree/bindings/edac/sifive-edac-l2.txt > > diff --git a/Documentation/devicetree/bindings/edac/sifive-edac-l2.txt b/Documentation/devicetree/bindings/edac/sifive-edac-l2.txt > new file mode 100644 > index 0000000..abce09f > --- /dev/null > +++ b/Documentation/devicetree/bindings/edac/sifive-edac-l2.txt > @@ -0,0 +1,31 @@ > +SiFive L2 Cache EDAC driver device tree bindings > +------------------------------------------------- > +This driver uses the EDAC framework to report L2 cache controller ECC errors. Bindings are for h/w blocks, not drivers. (And Boris may want a single driver, but bindings should reflect the h/w, not what Linux (currently) wants. Are the only controls for ECC? Are all the cache attributes discoverable (size, ways, line size, level, etc.)? > + > +- compatible: Should be "sifive,-ccache" and "sifive,ccache". > + Supported compatible strings are: > + "sifive,fu540-c000-ccache" for the SiFive cache controller v0 as integrated > + onto the SiFive FU540 chip, and "sifive,ccache0" for the SiFive > + cache controller v0 IP block with no chip integration tweaks. > + Please refer to sifive-blocks-ip-versioning.txt for details > + > +- interrupts: Must contain 3 entries for FU540 (DirError, DataError, and > + DataFail signals) or 4 entries for other chips (DirError, DirFail, DataError, > + and DataFail signals) 3 or 4, but you only have 1 chip compatible defined? > + > +- interrupt-parent: Must be core interrupt controller This is implied and could be in a parent node. > + > +- reg: Physical base address and size of L2 cache controller registers map > + A second range can indicate L2 Loosely Integrated Memory > + > +- reg-names: Names for the cells of reg, must contain "control" and "sideband" > + > +Example: > + > +cache-controller@2010000 { > + compatible = "sifive,fu540-c000-ccache", "sifive,ccache0"; > + interrupt-parent = <&plic>; > + interrupts = <1 2 3>; > + reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; > + reg-names = "control", "sideband"; > +}; > -- > 1.9.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller Date: Thu, 28 Mar 2019 08:16:57 -0500 Message-ID: <20190328131657.GA9056@bogus> References: <1552382461-13051-1-git-send-email-yash.shah@sifive.com> <1552382461-13051-2-git-send-email-yash.shah@sifive.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1552382461-13051-2-git-send-email-yash.shah@sifive.com> Sender: linux-kernel-owner@vger.kernel.org To: Yash Shah Cc: linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, palmer@sifive.com, paul.walmsley@sifive.com, linux-kernel@vger.kernel.org, mark.rutland@arm.com, aou@eecs.berkeley.edu, bp@alien8.de, mchehab@kernel.org, devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org On Tue, Mar 12, 2019 at 02:51:00PM +0530, Yash Shah wrote: > DT documentation for L2 cache controller added. > > Signed-off-by: Yash Shah > --- > .../devicetree/bindings/edac/sifive-edac-l2.txt | 31 ++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > create mode 100644 Documentation/devicetree/bindings/edac/sifive-edac-l2.txt > > diff --git a/Documentation/devicetree/bindings/edac/sifive-edac-l2.txt b/Documentation/devicetree/bindings/edac/sifive-edac-l2.txt > new file mode 100644 > index 0000000..abce09f > --- /dev/null > +++ b/Documentation/devicetree/bindings/edac/sifive-edac-l2.txt > @@ -0,0 +1,31 @@ > +SiFive L2 Cache EDAC driver device tree bindings > +------------------------------------------------- > +This driver uses the EDAC framework to report L2 cache controller ECC errors. Bindings are for h/w blocks, not drivers. (And Boris may want a single driver, but bindings should reflect the h/w, not what Linux (currently) wants. Are the only controls for ECC? Are all the cache attributes discoverable (size, ways, line size, level, etc.)? > + > +- compatible: Should be "sifive,-ccache" and "sifive,ccache". > + Supported compatible strings are: > + "sifive,fu540-c000-ccache" for the SiFive cache controller v0 as integrated > + onto the SiFive FU540 chip, and "sifive,ccache0" for the SiFive > + cache controller v0 IP block with no chip integration tweaks. > + Please refer to sifive-blocks-ip-versioning.txt for details > + > +- interrupts: Must contain 3 entries for FU540 (DirError, DataError, and > + DataFail signals) or 4 entries for other chips (DirError, DirFail, DataError, > + and DataFail signals) 3 or 4, but you only have 1 chip compatible defined? > + > +- interrupt-parent: Must be core interrupt controller This is implied and could be in a parent node. > + > +- reg: Physical base address and size of L2 cache controller registers map > + A second range can indicate L2 Loosely Integrated Memory > + > +- reg-names: Names for the cells of reg, must contain "control" and "sideband" > + > +Example: > + > +cache-controller@2010000 { > + compatible = "sifive,fu540-c000-ccache", "sifive,ccache0"; > + interrupt-parent = <&plic>; > + interrupts = <1 2 3>; > + reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; > + reg-names = "control", "sideband"; > +}; > -- > 1.9.1 >