From: Thierry Reding <thierry.reding@gmail.com>
To: "Randolph Maaßen" <gaireg@gaireg.de>
Cc: Laxman Dewangan <ldewangan@nvidia.com>,
Mark Brown <broonie@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
linux-spi@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] spi: tegra20-slink: change chip select action order
Date: Thu, 28 Mar 2019 17:34:16 +0100 [thread overview]
Message-ID: <20190328163416.GA31762@ulmo> (raw)
In-Reply-To: <20190326143050.26232-1-gaireg@gaireg.de>
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On Tue, Mar 26, 2019 at 03:30:50PM +0100, Randolph Maaßen wrote:
> To transfer via SPI the tegra20-slink driver first sets the command
> register, which contains the chip select value, and after that the
> command2 register, which contains the chip select line. This leads to a
> small spike in the chip selct 0 line between the set of the value and
> the selection of the chip select line.
>
> This commit changes the order of the register writes so that first the
> chip select line is chosen and then the value is set, removing the
> spike.
>
> Signed-off-by: Randolph Maaßen <gaireg@gaireg.de>
> ---
> drivers/spi/spi-tegra20-slink.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
With the typofix that Sowjanya pointed out, this patch is:
Acked-by: Thierry Reding <treding@nvidia.com>
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prev parent reply other threads:[~2019-03-28 16:34 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-26 14:30 [PATCH] spi: tegra20-slink: change chip select action order Randolph Maaßen
2019-03-26 14:44 ` Thierry Reding
2019-03-26 19:11 ` Sowjanya Komatineni
2019-03-28 16:34 ` Thierry Reding [this message]
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