* Re: [PATCH] drm/i915: fix i9xx irq enable/disable
2019-03-29 16:19 [PATCH] drm/i915: fix i9xx irq enable/disable Daniele Ceraolo Spurio
@ 2019-03-29 16:20 ` Daniele Ceraolo Spurio
2019-03-29 16:33 ` Chris Wilson
2019-03-29 16:32 ` Chris Wilson
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-29 16:20 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
On 3/29/19 9:19 AM, Daniele Ceraolo Spurio wrote:
> Those functions are used on gen4 as well and gen4 does have a non-RCS
> engine, so remove the BUG_ON and flip back the logic to what it was
> before the ENGINE_READ/WRITE update
>
> Fixes: baba6e572b38 ("drm/i915: take a reference to uncore in the engine and use it")
I'm not sure why this hasn't failed on our gen4 machines in CI. Are we
now so proactive in polling the HWSP that we just never enable the irqs?
Daniele
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++-------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
> 2 files changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 48ba4d61a4ae..586e75c9edf3 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -976,20 +976,16 @@ gen5_irq_disable(struct intel_engine_cs *engine)
> static void
> i9xx_irq_enable(struct intel_engine_cs *engine)
> {
> - GEM_BUG_ON(engine->id != RCS0);
> -
> engine->i915->irq_mask &= ~engine->irq_enable_mask;
> - ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask);
> - ENGINE_POSTING_READ(engine, RING_IMR);
> + intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask);
> + ENGINE_POSTING_READ_FW(engine, RING_IMR);
> }
>
> static void
> i9xx_irq_disable(struct intel_engine_cs *engine)
> {
> - GEM_BUG_ON(engine->id != RCS0);
> -
> engine->i915->irq_mask |= engine->irq_enable_mask;
> - ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask);
> + intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index e58d6f04177b..f34459ffaeb8 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -52,6 +52,7 @@ struct drm_printer;
> #define ENGINE_READ(...) __ENGINE_READ_OP(read, __VA_ARGS__)
> #define ENGINE_READ_FW(...) __ENGINE_READ_OP(read_fw, __VA_ARGS__)
> #define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read, __VA_ARGS__)
> +#define ENGINE_POSTING_READ_FW(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__)
>
> #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
> __ENGINE_REG_OP(read64_2x32, (engine__), \
>
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^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: fix i9xx irq enable/disable
2019-03-29 16:20 ` Daniele Ceraolo Spurio
@ 2019-03-29 16:33 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2019-03-29 16:33 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Paulo Zanoni
Quoting Daniele Ceraolo Spurio (2019-03-29 16:20:48)
>
>
> On 3/29/19 9:19 AM, Daniele Ceraolo Spurio wrote:
> > Those functions are used on gen4 as well and gen4 does have a non-RCS
> > engine, so remove the BUG_ON and flip back the logic to what it was
> > before the ENGINE_READ/WRITE update
> >
> > Fixes: baba6e572b38 ("drm/i915: take a reference to uncore in the engine and use it")
>
> I'm not sure why this hasn't failed on our gen4 machines in CI. Are we
> now so proactive in polling the HWSP that we just never enable the irqs?
It died on boot and so dropped out of CI. Our mechanism for catching
broken boots let us down here. Lessons learnt.
-Chris
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: fix i9xx irq enable/disable
2019-03-29 16:19 [PATCH] drm/i915: fix i9xx irq enable/disable Daniele Ceraolo Spurio
2019-03-29 16:20 ` Daniele Ceraolo Spurio
@ 2019-03-29 16:32 ` Chris Wilson
2019-03-29 16:41 ` Daniele Ceraolo Spurio
2019-03-29 16:35 ` Ville Syrjälä
2019-03-29 17:23 ` ✓ Fi.CI.BAT: success for " Patchwork
3 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2019-03-29 16:32 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Paulo Zanoni
Quoting Daniele Ceraolo Spurio (2019-03-29 16:19:00)
> Those functions are used on gen4 as well and gen4 does have a non-RCS
> engine, so remove the BUG_ON and flip back the logic to what it was
> before the ENGINE_READ/WRITE update
Oh, silly me, gm45.
> Fixes: baba6e572b38 ("drm/i915: take a reference to uncore in the engine and use it")
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++-------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
> 2 files changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 48ba4d61a4ae..586e75c9edf3 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -976,20 +976,16 @@ gen5_irq_disable(struct intel_engine_cs *engine)
> static void
> i9xx_irq_enable(struct intel_engine_cs *engine)
> {
> - GEM_BUG_ON(engine->id != RCS0);
> -
> engine->i915->irq_mask &= ~engine->irq_enable_mask;
> - ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask);
> - ENGINE_POSTING_READ(engine, RING_IMR);
> + intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask);
> + ENGINE_POSTING_READ_FW(engine, RING_IMR);
But now we are posting something else on vcs0. Make it an
intel_uncore_posting_read_fw(engine->uncore, IMR) to match.
-Chris
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^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: fix i9xx irq enable/disable
2019-03-29 16:32 ` Chris Wilson
@ 2019-03-29 16:41 ` Daniele Ceraolo Spurio
2019-03-29 16:50 ` Chris Wilson
0 siblings, 1 reply; 8+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-29 16:41 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Paulo Zanoni
On 3/29/19 9:32 AM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2019-03-29 16:19:00)
>> Those functions are used on gen4 as well and gen4 does have a non-RCS
>> engine, so remove the BUG_ON and flip back the logic to what it was
>> before the ENGINE_READ/WRITE update
>
> Oh, silly me, gm45.
>
>> Fixes: baba6e572b38 ("drm/i915: take a reference to uncore in the engine and use it")
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++-------
>> drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
>> 2 files changed, 4 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 48ba4d61a4ae..586e75c9edf3 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -976,20 +976,16 @@ gen5_irq_disable(struct intel_engine_cs *engine)
>> static void
>> i9xx_irq_enable(struct intel_engine_cs *engine)
>> {
>> - GEM_BUG_ON(engine->id != RCS0);
>> -
>> engine->i915->irq_mask &= ~engine->irq_enable_mask;
>> - ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask);
>> - ENGINE_POSTING_READ(engine, RING_IMR);
>> + intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask);
>> + ENGINE_POSTING_READ_FW(engine, RING_IMR);
>
> But now we are posting something else on vcs0. Make it an
> intel_uncore_posting_read_fw(engine->uncore, IMR) to match.
> -Chris
>
I thought so as well, but the pre-rework code did:
POSTING_READ_FW(RING_IMR(engine->mmio_base));
So I matched that.
Daniele
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: fix i9xx irq enable/disable
2019-03-29 16:41 ` Daniele Ceraolo Spurio
@ 2019-03-29 16:50 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2019-03-29 16:50 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Paulo Zanoni
Quoting Daniele Ceraolo Spurio (2019-03-29 16:41:55)
>
>
> On 3/29/19 9:32 AM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2019-03-29 16:19:00)
> >> Those functions are used on gen4 as well and gen4 does have a non-RCS
> >> engine, so remove the BUG_ON and flip back the logic to what it was
> >> before the ENGINE_READ/WRITE update
> >
> > Oh, silly me, gm45.
> >
> >> Fixes: baba6e572b38 ("drm/i915: take a reference to uncore in the engine and use it")
> >> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> >> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> >> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++-------
> >> drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
> >> 2 files changed, 4 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> index 48ba4d61a4ae..586e75c9edf3 100644
> >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> @@ -976,20 +976,16 @@ gen5_irq_disable(struct intel_engine_cs *engine)
> >> static void
> >> i9xx_irq_enable(struct intel_engine_cs *engine)
> >> {
> >> - GEM_BUG_ON(engine->id != RCS0);
> >> -
> >> engine->i915->irq_mask &= ~engine->irq_enable_mask;
> >> - ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask);
> >> - ENGINE_POSTING_READ(engine, RING_IMR);
> >> + intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask);
> >> + ENGINE_POSTING_READ_FW(engine, RING_IMR);
> >
> > But now we are posting something else on vcs0. Make it an
> > intel_uncore_posting_read_fw(engine->uncore, IMR) to match.
> > -Chris
> >
>
> I thought so as well, but the pre-rework code did:
>
> POSTING_READ_FW(RING_IMR(engine->mmio_base));
>
> So I matched that.
Go for that second fix with one patch. What could possibly go wrong?
-Chris
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: fix i9xx irq enable/disable
2019-03-29 16:19 [PATCH] drm/i915: fix i9xx irq enable/disable Daniele Ceraolo Spurio
2019-03-29 16:20 ` Daniele Ceraolo Spurio
2019-03-29 16:32 ` Chris Wilson
@ 2019-03-29 16:35 ` Ville Syrjälä
2019-03-29 17:23 ` ✓ Fi.CI.BAT: success for " Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjälä @ 2019-03-29 16:35 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, Paulo Zanoni
On Fri, Mar 29, 2019 at 09:19:00AM -0700, Daniele Ceraolo Spurio wrote:
> Those functions are used on gen4 as well and gen4 does have a non-RCS
> engine, so remove the BUG_ON and flip back the logic to what it was
> before the ENGINE_READ/WRITE update
>
> Fixes: baba6e572b38 ("drm/i915: take a reference to uncore in the engine and use it")
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++-------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
> 2 files changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 48ba4d61a4ae..586e75c9edf3 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -976,20 +976,16 @@ gen5_irq_disable(struct intel_engine_cs *engine)
> static void
> i9xx_irq_enable(struct intel_engine_cs *engine)
> {
> - GEM_BUG_ON(engine->id != RCS0);
> -
> engine->i915->irq_mask &= ~engine->irq_enable_mask;
> - ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask);
> - ENGINE_POSTING_READ(engine, RING_IMR);
> + intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask);
> + ENGINE_POSTING_READ_FW(engine, RING_IMR);
RING_IMR seems wrong still.
> }
>
> static void
> i9xx_irq_disable(struct intel_engine_cs *engine)
> {
> - GEM_BUG_ON(engine->id != RCS0);
> -
> engine->i915->irq_mask |= engine->irq_enable_mask;
> - ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask);
> + intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index e58d6f04177b..f34459ffaeb8 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -52,6 +52,7 @@ struct drm_printer;
> #define ENGINE_READ(...) __ENGINE_READ_OP(read, __VA_ARGS__)
> #define ENGINE_READ_FW(...) __ENGINE_READ_OP(read_fw, __VA_ARGS__)
> #define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read, __VA_ARGS__)
> +#define ENGINE_POSTING_READ_FW(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__)
>
> #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
> __ENGINE_REG_OP(read64_2x32, (engine__), \
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 8+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: fix i9xx irq enable/disable
2019-03-29 16:19 [PATCH] drm/i915: fix i9xx irq enable/disable Daniele Ceraolo Spurio
` (2 preceding siblings ...)
2019-03-29 16:35 ` Ville Syrjälä
@ 2019-03-29 17:23 ` Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-03-29 17:23 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: fix i9xx irq enable/disable
URL : https://patchwork.freedesktop.org/series/58748/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12633
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58748/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12633 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: PASS -> INCOMPLETE [fdo#109100]
* igt@gem_exec_store@basic-bsd1:
- fi-kbl-r: NOTRUN -> SKIP [fdo#109271] +41
* igt@gem_ringfill@basic-default-fd:
- fi-elk-e7500: NOTRUN -> SKIP [fdo#109271] +73
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_busy@basic-flip-c:
- fi-elk-e7500: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@vga-edid-read:
- fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@i915_selftest@live_uncore:
- fi-ivb-3770: DMESG-FAIL [fdo#110210] -> PASS
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +2
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (46 -> 41)
------------------------------
Additional (3): fi-hsw-4770r fi-kbl-r fi-elk-e7500
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5837 -> Patchwork_12633
CI_DRM_5837: 1a35af6fa0d612425e325024cbac10e6fa9a9cd5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4912: 66deae8b6fa69540f069d6551cd22013f5343948 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12633: 14f03544a70eaf2751537cb481fe26ad01ad6b63 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
14f03544a70e drm/i915: fix i9xx irq enable/disable
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12633/
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^ permalink raw reply [flat|nested] 8+ messages in thread