Re: Perf counters on SiFive FU540-C000

[Alan Kao <alankao@andestech.com>]

Hi,

On Tue, Apr 02, 2019 at 10:57:14AM -0700, Palmer Dabbelt wrote:
> On Sun, 31 Mar 2019 07:37:32 PDT (-0700), laanwj@gmail.com wrote:
> >Hello,
> >
> >I'm planning on doing some optimization work for RISC-V, so I'd like to add
> >perf support for the performance counters on the FU540-C000—as described in
> >Section 4.10 of the "SiFive FU540-C000 Manual".
> 
> That would be great, thanks!
> 
> >These are very basic: CSRs mhpmevent3 and mhpmevent4 can be used to choose a category
> >(Instruction Commit Events, Microarchitectural Events, Memory System Events), then
> >from these categories a bitmask of events can be set that will increase the associated
> >counter when they happen. I don't understand the rationale for counting multiple
> >kinds of events in one register, so from what I understand, two counters can be
> >supported at once in the perf interface.
> 
> The idea here is to allow users to have different performance counter
> granularities.  For example, users might want to count all pipeline flushes
> (maybe their framework defines that as a possible counter type) or may want
> to specifically indicate which sort of pipeline flush should be counted.
> 
> >I found some documentation about platform specfic counters in Documentation/riscv/pmu.txt,
> >hopefully this is enough to get me started.
> >(If someone started work on this, please let me know)
> 
> Someone from Andes had patches out to add support for their performance
> counters a while ago.  The issue there was that the performance counter
> implementation was chosen at compile time, but it should really be detected
> at run time via some platform-specific mechanism (ie, device tree).

PMU detection was one of the problems, and should have been solved in previous
patches.  For the rest of the problems, Documentation/riscv/pmu.txt should
serve as a good guide.

> Aside from that I think the only issue was how to expose these to userspace
> in a sane fashion, which is something I thought would be quite tricky.  IIRC
> someone managed to convince me that there was a really simple scheme for
> doing this, but I don't remember what it was.

The corresponding userspace tool is in tools/perf.  Once one finishes the kernel
part, the work left for userspace perf will be the symbolization of PMU raw
events.  The preliminary patch supports common counters only, so I believe this
will be the first platform-specific PMU in RISC-V.

Alan

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