Re: [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Wed, Apr 03, 2019 at 04:35:33PM -0700, José Roberto de Souza wrote:
> Turn out it is not a DMC bug it is actually a HW one, so this
> workaround will be needed for current gens, lets update the comment
> and remove the FIXME.

Do we have a Wa #number for this? p[art of workaround page
or just part of programming sequence?

> 
> BSpec: 7723
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index ec874d802d48..c80bb3003a7d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -531,10 +531,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  		val |= EDP_PSR2_TP2_TIME_2500us;
>  
>  	/*
> -	 * FIXME: There is probably a issue in DMC firmwares(icl_dmc_ver1_07.bin
> -	 * and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after
> -	 * exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now
> -	 * lets workaround the issue by cleaning PSR_CTL before enable PSR2.
> +	 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
> +	 * recommending keep this bit unset while PSR2 is enabled.
>  	 */
>  	I915_WRITE(EDP_PSR_CTL, 0);
>  
> -- 
> 2.21.0
> 
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