From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Wu Date: Thu, 4 Apr 2019 11:55:53 +0800 Subject: [U-Boot] [PATCH v2 06/10] pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' drive strength In-Reply-To: <20190404035140.3721-1-david.wu@rock-chips.com> References: <20190404035140.3721-1-david.wu@rock-chips.com> Message-ID: <20190404035553.4205-1-david.wu@rock-chips.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de RK3288 pmu_gpio0 drive strength setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu --- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index c52711914e..6f489d2d54 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -141,8 +141,14 @@ static int rk3288_set_drive(struct rockchip_pin_bank *bank, return ret; } - /* enable the write to the equivalent lower bits */ - data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + if (bank->bank_num == 0) { + regmap_read(regmap, reg, &data); + data &= ~(((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << bit); + } else { + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + } + data |= (ret << bit); ret = regmap_write(regmap, reg, data); return ret; -- 2.19.1