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From: Dmitry Osipenko <digetx@gmail.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Joseph Lo <josephl@nvidia.com>
Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v1 1/5] clk: tegra: emc: Don't enable EMC clock manually
Date: Fri, 12 Apr 2019 01:02:26 +0300	[thread overview]
Message-ID: <20190411220230.21726-2-digetx@gmail.com> (raw)
In-Reply-To: <20190411220230.21726-1-digetx@gmail.com>

The EMC clock marked as critical, hence it is already enabled at the
registration time.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/clk/tegra/clk-emc.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-emc.c b/drivers/clk/tegra/clk-emc.c
index 0621a3a82ea6..23416982e7c7 100644
--- a/drivers/clk/tegra/clk-emc.c
+++ b/drivers/clk/tegra/clk-emc.c
@@ -532,7 +532,5 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
 	/* Allow debugging tools to see the EMC clock */
 	clk_register_clkdev(clk, "emc", "tegra-clk-debug");
 
-	clk_prepare_enable(clk);
-
 	return clk;
 };
-- 
2.21.0


  reply	other threads:[~2019-04-11 22:04 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-11 22:02 [PATCH v1 0/5] clk: tegra: EMC/MC clock fixes and improvements Dmitry Osipenko
2019-04-11 22:02 ` Dmitry Osipenko [this message]
2019-04-11 22:02 ` [PATCH v1 2/5] clk: tegra: emc: Support multiple ram codes parsing Dmitry Osipenko
2019-04-11 22:02 ` [PATCH v1 3/5] clk: tegra: emc: Fix EMC max-rate clamping Dmitry Osipenko
2019-04-11 22:02 ` [PATCH v1 4/5] clk: tegra: emc: Replace BUG() with WARN_ONCE() Dmitry Osipenko
2019-04-11 22:02 ` [PATCH v1 5/5] clk: tegra: divider: Mark Memory Controller clock as read-only Dmitry Osipenko
2019-04-12 13:54   ` Dmitry Osipenko

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