Re: [PATCH 20/30] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct

[Thierry Reding <thierry.reding@gmail.com>]

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On Thu, Apr 11, 2019 at 10:33:45PM +0530, Manikanta Maddireddy wrote:
> Tegra186 and Tegra30 have three PCIe root ports. AFI_PEX2_CTRL register
> is defined for third root port. Offset of this register in Tegra186 is
> different from Tegra30, so add offset as part of soc data structure.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>  drivers/pci/controller/pci-tegra.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)

Acked-by: Thierry Reding <treding@nvidia.com>

> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> index 11be88a394e3..8fdc7934d4c9 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -169,7 +169,6 @@
>  
>  #define AFI_PEX0_CTRL			0x110
>  #define AFI_PEX1_CTRL			0x118
> -#define AFI_PEX2_CTRL			0x128
>  #define  AFI_PEX_CTRL_RST		(1 << 0)
>  #define  AFI_PEX_CTRL_CLKREQ_EN		(1 << 1)
>  #define  AFI_PEX_CTRL_REFCLK_EN		(1 << 3)
> @@ -307,6 +306,7 @@ struct tegra_pcie_soc {
>  	unsigned int num_ports;
>  	const struct tegra_pcie_port_soc *ports;
>  	unsigned int msi_base_shift;
> +	unsigned long afi_pex2_ctrl;
>  	u32 pads_pll_ctl;
>  	u32 tx_ref_sel;
>  	u32 pads_refclk_cfg0;
> @@ -516,6 +516,7 @@ static struct pci_ops tegra_pcie_ops = {
>  
>  static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
>  {
> +	const struct tegra_pcie_soc *soc = port->pcie->soc;
>  	unsigned long ret = 0;
>  
>  	switch (port->index) {
> @@ -528,7 +529,7 @@ static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
>  		break;
>  
>  	case 2:
> -		ret = AFI_PEX2_CTRL;
> +		ret = soc->afi_pex2_ctrl;
>  		break;
>  	}
>  
> @@ -2439,6 +2440,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
>  	.num_ports = 2,
>  	.ports = tegra20_pcie_ports,
>  	.msi_base_shift = 0,
> +	.afi_pex2_ctrl = 0x128,
>  	.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
>  	.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
>  	.pads_refclk_cfg0 = 0xfa5cfa5c,
> @@ -2548,6 +2550,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
>  	.num_ports = 3,
>  	.ports = tegra186_pcie_ports,
>  	.msi_base_shift = 8,
> +	.afi_pex2_ctrl = 0x19c,
>  	.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
>  	.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
>  	.pads_refclk_cfg0 = 0x80b880b8,
> -- 
> 2.17.1
> 

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