From: Sudeep Holla <sudeep.holla@arm.com>
To: Marek Bykowski <marek.bykowski@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org,
Sudeep Holla <sudeep.holla@arm.com>
Subject: Re: L3 cache way-locking memory zone
Date: Mon, 15 Apr 2019 15:07:02 +0100 [thread overview]
Message-ID: <20190415140645.GA24249@e107155-lin> (raw)
In-Reply-To: <20190415153849.358d78a9@gmail.com>
On Mon, Apr 15, 2019 at 03:38:49PM +0200, Marek Bykowski wrote:
> Hi All,
>
> Would the mainline be interested in definition/creation of the memory
> zone to L3 cache way-locking memory range/s?
>
> We have this implemented around the system featuring Cortex-A53/57 and
> the CCN-512/504 with L3 cache (LLC) configured to way-locking. The
> benefits arising are a faster memory access.
>
> If you reckon this is something of interest I can share more
> details, patch, use case, etc.
>
I am sure many will be interested. But depends on how generic is the
solution ? It's extremely difficult to come up with one.
ARM has Memory System Resource Partitioning(MPAM) to solve this in a
generic way. I know it may not solve issue for current platforms, but
just thought it's worth pointing out so that people are aware of it.
--
Regards,
Sudeep
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next prev parent reply other threads:[~2019-04-15 14:07 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-15 13:38 L3 cache way-locking memory zone Marek Bykowski
2019-04-15 14:07 ` Sudeep Holla [this message]
2019-04-16 10:32 ` Marek Bykowski
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