From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH v3 3/3] DRM: Add KMS driver for the Ingenic JZ47xx SoCs Date: Mon, 15 Apr 2019 18:07:46 +0200 Message-ID: <20190415160746.GE2665@phenom.ffwll.local> References: <20190414200824.28348-1-paul@crapouillou.net> <20190414200824.28348-3-paul@crapouillou.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20190414200824.28348-3-paul@crapouillou.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Paul Cercueil Cc: Mark Rutland , devicetree@vger.kernel.org, od@zcrc.me, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Maxime Ripard , Rob Herring , Sean Paul List-Id: devicetree@vger.kernel.org T24gU3VuLCBBcHIgMTQsIDIwMTkgYXQgMTA6MDg6MjRQTSArMDIwMCwgUGF1bCBDZXJjdWVpbCB3 cm90ZToKPiBBZGQgYSBLTVMgZHJpdmVyIGZvciB0aGUgSW5nZW5pYyBKWjQ3eHggZmFtaWx5IG9m IFNvQ3MuCj4gVGhpcyBkcml2ZXIgaXMgbWVhbnQgdG8gcmVwbGFjZSB0aGUgYWdpbmcgano0NzQw LWZiIGRyaXZlci4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBQYXVsIENlcmN1ZWlsIDxwYXVsQGNyYXBv dWlsbG91Lm5ldD4KPiBUZXN0ZWQtYnk6IEFydHVyIFJvamVrIDxjb250YWN0QGFydHVyLXJvamVr LmV1PgoKUGxlYXNlIHB1dCBzb21ld2hlcmUgaW4geW91ciBjb21taXQgbWVzc2FnZSB3aHkgeW91 J3JlIG5vdCB1c2luZyB0aGUKc2ltcGxlIHBpcGUgaGVscGVycyAtIEkgaGFkIHRvIHJlY2hlY2sg dGhhdCBmcm9tIHByZXZpb3VzIGRpc2N1c3Npb25zIDotKQotRGFuaWVsCgo+IC0tLQo+IAo+IE5v dGVzOgo+ICAgICB2MjogLSBSZW1vdmUgY3VzdG9tIGhhbmRsaW5nIG9mIHBhbmVsLiBUaGUgcGFu ZWwgaXMgbm93IGRpc2NvdmVyZWQgdXNpbmcKPiAgICAgCSAgdGhlIHN0YW5kYXJkIEFQSS4KPiAg ICAgCS0gTG90cyBvZiBzbWFsbCB0d2Vha3Mgc3VnZ2VzdGVkIGJ5IHVwc3RyZWFtCj4gICAgIAo+ ICAgICB2MzogLSBVc2UgZGV2bV9kcm1fZGV2X2luaXQoKQo+ICAgICAgICAgLSBVcGRhdGUgY29t cGF0aWJsZSBzdHJpbmdzIHRvIC1sY2QgaW5zdGVhZCBvZiAtZHJtCj4gICAgIAktIEFkZCBkZXN0 cm95KCkgY2FsbGJhY2tzIHRvIHBsYW5lIGFuZCBjcnRjCj4gICAgIAktIFRoZSBpbmdlbmljLGxj ZC1tb2RlIGlzIG5vdyByZWFkIGZyb20gdGhlIGJyaWRnZSdzIERUIG5vZGUKPiAKPiAgZHJpdmVy cy9ncHUvZHJtL0tjb25maWcgICAgICAgICAgICAgICB8ICAgMiArCj4gIGRyaXZlcnMvZ3B1L2Ry bS9NYWtlZmlsZSAgICAgICAgICAgICAgfCAgIDEgKwo+ICBkcml2ZXJzL2dwdS9kcm0vaW5nZW5p Yy9LY29uZmlnICAgICAgIHwgIDE2ICsKPiAgZHJpdmVycy9ncHUvZHJtL2luZ2VuaWMvTWFrZWZp bGUgICAgICB8ICAgMSArCj4gIGRyaXZlcnMvZ3B1L2RybS9pbmdlbmljL2luZ2VuaWMtZHJtLmMg fCA4MDggKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKwo+ICA1IGZpbGVzIGNoYW5n ZWQsIDgyOCBpbnNlcnRpb25zKCspCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9k cm0vaW5nZW5pYy9LY29uZmlnCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0v aW5nZW5pYy9NYWtlZmlsZQo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL2lu Z2VuaWMvaW5nZW5pYy1kcm0uYwo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vS2Nv bmZpZyBiL2RyaXZlcnMvZ3B1L2RybS9LY29uZmlnCj4gaW5kZXggMzlkNWY3NTYyZjFjLi42ODYz MjIzYzYxZDUgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL0tjb25maWcKPiArKysgYi9k cml2ZXJzL2dwdS9kcm0vS2NvbmZpZwo+IEBAIC0zMDcsNiArMzA3LDggQEAgc291cmNlICJkcml2 ZXJzL2dwdS9kcm0vc3RpL0tjb25maWciCj4gIAo+ICBzb3VyY2UgImRyaXZlcnMvZ3B1L2RybS9p bXgvS2NvbmZpZyIKPiAgCj4gK3NvdXJjZSAiZHJpdmVycy9ncHUvZHJtL2luZ2VuaWMvS2NvbmZp ZyIKPiArCj4gIHNvdXJjZSAiZHJpdmVycy9ncHUvZHJtL3YzZC9LY29uZmlnIgo+ICAKPiAgc291 cmNlICJkcml2ZXJzL2dwdS9kcm0vdmM0L0tjb25maWciCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMv Z3B1L2RybS9NYWtlZmlsZSBiL2RyaXZlcnMvZ3B1L2RybS9NYWtlZmlsZQo+IGluZGV4IDNkMGM3 NWNkNjg3Yy4uMWMyYWNhNzk2NWJkIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9NYWtl ZmlsZQo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9NYWtlZmlsZQo+IEBAIC05NSw2ICs5NSw3IEBA IG9iai0kKENPTkZJR19EUk1fVEVHUkEpICs9IHRlZ3JhLwo+ICBvYmotJChDT05GSUdfRFJNX1NU TSkgKz0gc3RtLwo+ICBvYmotJChDT05GSUdfRFJNX1NUSSkgKz0gc3RpLwo+ICBvYmotJChDT05G SUdfRFJNX0lNWCkgKz0gaW14Lwo+ICtvYmotJChDT05GSUdfRFJNX0lOR0VOSUMpICs9IGluZ2Vu aWMvCj4gIG9iai0kKENPTkZJR19EUk1fTUVESUFURUspICs9IG1lZGlhdGVrLwo+ICBvYmotJChD T05GSUdfRFJNX01FU09OKQkrPSBtZXNvbi8KPiAgb2JqLXkJCQkrPSBpMmMvCj4gZGlmZiAtLWdp dCBhL2RyaXZlcnMvZ3B1L2RybS9pbmdlbmljL0tjb25maWcgYi9kcml2ZXJzL2dwdS9kcm0vaW5n ZW5pYy9LY29uZmlnCj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPiBpbmRleCAwMDAwMDAwMDAwMDAu LmQ4MmMzZDM3ZWM5Ywo+IC0tLSAvZGV2L251bGwKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaW5n ZW5pYy9LY29uZmlnCj4gQEAgLTAsMCArMSwxNiBAQAo+ICtjb25maWcgRFJNX0lOR0VOSUMKPiAr CXRyaXN0YXRlICJEUk0gU3VwcG9ydCBmb3IgSW5nZW5pYyBTb0NzIgo+ICsJZGVwZW5kcyBvbiBN SVBTIHx8IENPTVBJTEVfVEVTVAo+ICsJZGVwZW5kcyBvbiBEUk0KPiArCWRlcGVuZHMgb24gQ01B Cj4gKwlkZXBlbmRzIG9uIE9GCj4gKwlzZWxlY3QgRFJNX0JSSURHRQo+ICsJc2VsZWN0IERSTV9Q QU5FTF9CUklER0UKPiArCXNlbGVjdCBEUk1fS01TX0hFTFBFUgo+ICsJc2VsZWN0IERSTV9LTVNf Q01BX0hFTFBFUgo+ICsJc2VsZWN0IERSTV9HRU1fQ01BX0hFTFBFUgo+ICsJc2VsZWN0IFZUX0hX X0NPTlNPTEVfQklORElORyBpZiBGUkFNRUJVRkZFUl9DT05TT0xFCj4gKwloZWxwCj4gKwkgIENo b29zZSB0aGlzIG9wdGlvbiBmb3IgRFJNIHN1cHBvcnQgZm9yIHRoZSBJbmdlbmljIFNvQ3MuCj4g Kwo+ICsJICBJZiBNIGlzIHNlbGVjdGVkIHRoZSBtb2R1bGUgd2lsbCBiZSBjYWxsZWQgaW5nZW5p Yy1kcm0uCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pbmdlbmljL01ha2VmaWxlIGIv ZHJpdmVycy9ncHUvZHJtL2luZ2VuaWMvTWFrZWZpbGUKPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+ IGluZGV4IDAwMDAwMDAwMDAwMC4uMTFjYWM0MmNlMGJiCj4gLS0tIC9kZXYvbnVsbAo+ICsrKyBi L2RyaXZlcnMvZ3B1L2RybS9pbmdlbmljL01ha2VmaWxlCj4gQEAgLTAsMCArMSBAQAo+ICtvYmot JChDT05GSUdfRFJNX0lOR0VOSUMpICs9IGluZ2VuaWMtZHJtLm8KPiBkaWZmIC0tZ2l0IGEvZHJp dmVycy9ncHUvZHJtL2luZ2VuaWMvaW5nZW5pYy1kcm0uYyBiL2RyaXZlcnMvZ3B1L2RybS9pbmdl bmljL2luZ2VuaWMtZHJtLmMKPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAwMDAwMDAw MDAwMC4uNmI1MmVmMmY5NzkwCj4gLS0tIC9kZXYvbnVsbAo+ICsrKyBiL2RyaXZlcnMvZ3B1L2Ry bS9pbmdlbmljL2luZ2VuaWMtZHJtLmMKPiBAQCAtMCwwICsxLDgwOCBAQAo+ICsvLyBTUERYLUxp Y2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMAo+ICsvLwo+ICsvLyBJbmdlbmljIEpaNDd4eCBLTVMg ZHJpdmVyCj4gKy8vCj4gKy8vIENvcHlyaWdodCAoQykgMjAxOSwgUGF1bCBDZXJjdWVpbCA8cGF1 bEBjcmFwb3VpbGxvdS5uZXQ+Cj4gKwo+ICsjaW5jbHVkZSA8bGludXgvY2xrLmg+Cj4gKyNpbmNs dWRlIDxsaW51eC9kbWEtbWFwcGluZy5oPgo+ICsjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+Cj4g KyNpbmNsdWRlIDxsaW51eC9vZl9kZXZpY2UuaD4KPiArI2luY2x1ZGUgPGxpbnV4L3BsYXRmb3Jt X2RldmljZS5oPgo+ICsjaW5jbHVkZSA8bGludXgvcmVnbWFwLmg+Cj4gKwo+ICsjaW5jbHVkZSA8 ZHJtL2RybV9hdG9taWMuaD4KPiArI2luY2x1ZGUgPGRybS9kcm1fYXRvbWljX2hlbHBlci5oPgo+ ICsjaW5jbHVkZSA8ZHJtL2RybV9jcnRjLmg+Cj4gKyNpbmNsdWRlIDxkcm0vZHJtX2NydGNfaGVs cGVyLmg+Cj4gKyNpbmNsdWRlIDxkcm0vZHJtX2Rydi5oPgo+ICsjaW5jbHVkZSA8ZHJtL2RybV9n ZW1fY21hX2hlbHBlci5oPgo+ICsjaW5jbHVkZSA8ZHJtL2RybV9mYl9jbWFfaGVscGVyLmg+Cj4g KyNpbmNsdWRlIDxkcm0vZHJtX2ZiX2hlbHBlci5oPgo+ICsjaW5jbHVkZSA8ZHJtL2RybV9mb3Vy Y2MuaD4KPiArI2luY2x1ZGUgPGRybS9kcm1fZ2VtX2ZyYW1lYnVmZmVyX2hlbHBlci5oPgo+ICsj aW5jbHVkZSA8ZHJtL2RybV9pcnEuaD4KPiArI2luY2x1ZGUgPGRybS9kcm1fb2YuaD4KPiArI2lu Y2x1ZGUgPGRybS9kcm1fcGFuZWwuaD4KPiArI2luY2x1ZGUgPGRybS9kcm1fcGxhbmUuaD4KPiAr I2luY2x1ZGUgPGRybS9kcm1fcGxhbmVfaGVscGVyLmg+Cj4gKyNpbmNsdWRlIDxkcm0vZHJtX3By b2JlX2hlbHBlci5oPgo+ICsjaW5jbHVkZSA8ZHJtL2RybV92YmxhbmsuaD4KPiArCj4gKyNpbmNs dWRlIDxkdC1iaW5kaW5ncy9kaXNwbGF5L2luZ2VuaWMsZHJtLmg+Cj4gKwo+ICsjZGVmaW5lIEpa X1JFR19MQ0RfQ0ZHCQkweDAwCj4gKyNkZWZpbmUgSlpfUkVHX0xDRF9WU1lOQwkweDA0Cj4gKyNk ZWZpbmUgSlpfUkVHX0xDRF9IU1lOQwkweDA4Cj4gKyNkZWZpbmUgSlpfUkVHX0xDRF9WQVQJCTB4 MEMKPiArI2RlZmluZSBKWl9SRUdfTENEX0RBSAkJMHgxMAo+ICsjZGVmaW5lIEpaX1JFR19MQ0Rf REFWCQkweDE0Cj4gKyNkZWZpbmUgSlpfUkVHX0xDRF9QUwkJMHgxOAo+ICsjZGVmaW5lIEpaX1JF R19MQ0RfQ0xTCQkweDFDCj4gKyNkZWZpbmUgSlpfUkVHX0xDRF9TUEwJCTB4MjAKPiArI2RlZmlu ZSBKWl9SRUdfTENEX1JFVgkJMHgyNAo+ICsjZGVmaW5lIEpaX1JFR19MQ0RfQ1RSTAkJMHgzMAo+ ICsjZGVmaW5lIEpaX1JFR19MQ0RfU1RBVEUJMHgzNAo+ICsjZGVmaW5lIEpaX1JFR19MQ0RfSUlE CQkweDM4Cj4gKyNkZWZpbmUgSlpfUkVHX0xDRF9EQTAJCTB4NDAKPiArI2RlZmluZSBKWl9SRUdf TENEX1NBMAkJMHg0NAo+ICsjZGVmaW5lIEpaX1JFR19MQ0RfRklEMAkJMHg0OAo+ICsjZGVmaW5l IEpaX1JFR19MQ0RfQ01EMAkJMHg0Qwo+ICsjZGVmaW5lIEpaX1JFR19MQ0RfREExCQkweDUwCj4g KyNkZWZpbmUgSlpfUkVHX0xDRF9TQTEJCTB4NTQKPiArI2RlZmluZSBKWl9SRUdfTENEX0ZJRDEJ CTB4NTgKPiArI2RlZmluZSBKWl9SRUdfTENEX0NNRDEJCTB4NUMKPiArCj4gKyNkZWZpbmUgSlpf TENEX0NGR19TTENECQkJQklUKDMxKQo+ICsjZGVmaW5lIEpaX0xDRF9DRkdfUFNfRElTQUJMRQkJ QklUKDIzKQo+ICsjZGVmaW5lIEpaX0xDRF9DRkdfQ0xTX0RJU0FCTEUJCUJJVCgyMikKPiArI2Rl ZmluZSBKWl9MQ0RfQ0ZHX1NQTF9ESVNBQkxFCQlCSVQoMjEpCj4gKyNkZWZpbmUgSlpfTENEX0NG R19SRVZfRElTQUJMRQkJQklUKDIwKQo+ICsjZGVmaW5lIEpaX0xDRF9DRkdfSFNZTkNNCQlCSVQo MTkpCj4gKyNkZWZpbmUgSlpfTENEX0NGR19QQ0xLTQkJQklUKDE4KQo+ICsjZGVmaW5lIEpaX0xD RF9DRkdfSU5WCQkJQklUKDE3KQo+ICsjZGVmaW5lIEpaX0xDRF9DRkdfU1lOQ19ESVIJCUJJVCgx NikKPiArI2RlZmluZSBKWl9MQ0RfQ0ZHX1BTX1BPTEFSSVRZCQlCSVQoMTUpCj4gKyNkZWZpbmUg SlpfTENEX0NGR19DTFNfUE9MQVJJVFkJCUJJVCgxNCkKPiArI2RlZmluZSBKWl9MQ0RfQ0ZHX1NQ TF9QT0xBUklUWQkJQklUKDEzKQo+ICsjZGVmaW5lIEpaX0xDRF9DRkdfUkVWX1BPTEFSSVRZCQlC SVQoMTIpCj4gKyNkZWZpbmUgSlpfTENEX0NGR19IU1lOQ19BQ1RJVkVfTE9XCUJJVCgxMSkKPiAr I2RlZmluZSBKWl9MQ0RfQ0ZHX1BDTEtfRkFMTElOR19FREdFCUJJVCgxMCkKPiArI2RlZmluZSBK Wl9MQ0RfQ0ZHX0RFX0FDVElWRV9MT1cJQklUKDkpCj4gKyNkZWZpbmUgSlpfTENEX0NGR19WU1lO Q19BQ1RJVkVfTE9XCUJJVCg4KQo+ICsjZGVmaW5lIEpaX0xDRF9DRkdfMThfQklUCQlCSVQoNykK PiArI2RlZmluZSBKWl9MQ0RfQ0ZHX1BEVwkJCShCSVQoNSkgfCBCSVQoNCkpCj4gKyNkZWZpbmUg SlpfTENEX0NGR19NT0RFX01BU0sJCTB4Zgo+ICsKPiArI2RlZmluZSBKWl9MQ0RfVlNZTkNfVlBT X09GRlNFVAkJMTYKPiArI2RlZmluZSBKWl9MQ0RfVlNZTkNfVlBFX09GRlNFVAkJMAo+ICsKPiAr I2RlZmluZSBKWl9MQ0RfSFNZTkNfSFBTX09GRlNFVAkJMTYKPiArI2RlZmluZSBKWl9MQ0RfSFNZ TkNfSFBFX09GRlNFVAkJMAo+ICsKPiArI2RlZmluZSBKWl9MQ0RfVkFUX0hUX09GRlNFVAkJMTYK PiArI2RlZmluZSBKWl9MQ0RfVkFUX1ZUX09GRlNFVAkJMAo+ICsKPiArI2RlZmluZSBKWl9MQ0Rf REFIX0hEU19PRkZTRVQJCTE2Cj4gKyNkZWZpbmUgSlpfTENEX0RBSF9IREVfT0ZGU0VUCQkwCj4g Kwo+ICsjZGVmaW5lIEpaX0xDRF9EQVZfVkRTX09GRlNFVAkJMTYKPiArI2RlZmluZSBKWl9MQ0Rf REFWX1ZERV9PRkZTRVQJCTAKPiArCj4gKyNkZWZpbmUgSlpfTENEX0NUUkxfQlVSU1RfNAkJKDB4 MCA8PCAyOCkKPiArI2RlZmluZSBKWl9MQ0RfQ1RSTF9CVVJTVF84CQkoMHgxIDw8IDI4KQo+ICsj ZGVmaW5lIEpaX0xDRF9DVFJMX0JVUlNUXzE2CQkoMHgyIDw8IDI4KQo+ICsjZGVmaW5lIEpaX0xD RF9DVFJMX1JHQjU1NQkJQklUKDI3KQo+ICsjZGVmaW5lIEpaX0xDRF9DVFJMX09GVVAJCUJJVCgy NikKPiArI2RlZmluZSBKWl9MQ0RfQ1RSTF9GUkNfR1JBWVNDQUxFXzE2CSgweDAgPDwgMjQpCj4g KyNkZWZpbmUgSlpfTENEX0NUUkxfRlJDX0dSQVlTQ0FMRV80CSgweDEgPDwgMjQpCj4gKyNkZWZp bmUgSlpfTENEX0NUUkxfRlJDX0dSQVlTQ0FMRV8yCSgweDIgPDwgMjQpCj4gKyNkZWZpbmUgSlpf TENEX0NUUkxfUEREX01BU0sJCSgweGZmIDw8IDE2KQo+ICsjZGVmaW5lIEpaX0xDRF9DVFJMX0VP Rl9JUlEJCUJJVCgxMykKPiArI2RlZmluZSBKWl9MQ0RfQ1RSTF9TT0ZfSVJRCQlCSVQoMTIpCj4g KyNkZWZpbmUgSlpfTENEX0NUUkxfT0ZVX0lSUQkJQklUKDExKQo+ICsjZGVmaW5lIEpaX0xDRF9D VFJMX0lGVTBfSVJRCQlCSVQoMTApCj4gKyNkZWZpbmUgSlpfTENEX0NUUkxfSUZVMV9JUlEJCUJJ VCg5KQo+ICsjZGVmaW5lIEpaX0xDRF9DVFJMX0REX0lSUQkJQklUKDgpCj4gKyNkZWZpbmUgSlpf TENEX0NUUkxfUUREX0lSUQkJQklUKDcpCj4gKyNkZWZpbmUgSlpfTENEX0NUUkxfUkVWRVJTRV9F TkRJQU4JQklUKDYpCj4gKyNkZWZpbmUgSlpfTENEX0NUUkxfTFNCX0ZJU1JUCQlCSVQoNSkKPiAr I2RlZmluZSBKWl9MQ0RfQ1RSTF9ESVNBQkxFCQlCSVQoNCkKPiArI2RlZmluZSBKWl9MQ0RfQ1RS TF9FTkFCTEUJCUJJVCgzKQo+ICsjZGVmaW5lIEpaX0xDRF9DVFJMX0JQUF8xCQkweDAKPiArI2Rl ZmluZSBKWl9MQ0RfQ1RSTF9CUFBfMgkJMHgxCj4gKyNkZWZpbmUgSlpfTENEX0NUUkxfQlBQXzQJ CTB4Mgo+ICsjZGVmaW5lIEpaX0xDRF9DVFJMX0JQUF84CQkweDMKPiArI2RlZmluZSBKWl9MQ0Rf Q1RSTF9CUFBfMTVfMTYJCTB4NAo+ICsjZGVmaW5lIEpaX0xDRF9DVFJMX0JQUF8xOF8yNAkJMHg1 Cj4gKyNkZWZpbmUgSlpfTENEX0NUUkxfQlBQX01BU0sJCShKWl9MQ0RfQ1RSTF9SR0I1NTUgfCAo MHg3IDw8IDApKQo+ICsKPiArI2RlZmluZSBKWl9MQ0RfQ01EX1NPRl9JUlEJCUJJVCgzMSkKPiAr I2RlZmluZSBKWl9MQ0RfQ01EX0VPRl9JUlEJCUJJVCgzMCkKPiArI2RlZmluZSBKWl9MQ0RfQ01E X0VOQUJMRV9QQUwJCUJJVCgyOCkKPiArCj4gKyNkZWZpbmUgSlpfTENEX1NZTkNfTUFTSwkJMHgz ZmYKPiArCj4gKyNkZWZpbmUgSlpfTENEX1NUQVRFX0VPRl9JUlEJCUJJVCg1KQo+ICsjZGVmaW5l IEpaX0xDRF9TVEFURV9TT0ZfSVJRCQlCSVQoNCkKPiArI2RlZmluZSBKWl9MQ0RfU1RBVEVfRElT QUJMRUQJCUJJVCgwKQo+ICsKPiArc3RydWN0IGluZ2VuaWNfZG1hX2h3ZGVzYyB7Cj4gKwl1MzIg bmV4dDsKPiArCXUzMiBhZGRyOwo+ICsJdTMyIGlkOwo+ICsJdTMyIGNtZDsKPiArfSBfX3BhY2tl ZDsKPiArCj4gK3N0cnVjdCBqel9zb2NfaW5mbyB7Cj4gKwlib29sIG5lZWRzX2Rldl9jbGs7Cj4g K307Cj4gKwo+ICtzdHJ1Y3QgaW5nZW5pY19kcm0gewo+ICsJc3RydWN0IGRybV9kZXZpY2UgZHJt Owo+ICsJc3RydWN0IGRybV9wbGFuZSBwcmltYXJ5Owo+ICsJc3RydWN0IGRybV9jcnRjIGNydGM7 Cj4gKwlzdHJ1Y3QgZHJtX2VuY29kZXIgZW5jb2RlcjsKPiArCj4gKwlzdHJ1Y3QgZGV2aWNlICpk ZXY7Cj4gKwlzdHJ1Y3QgcmVnbWFwICptYXA7Cj4gKwlzdHJ1Y3QgY2xrICpsY2RfY2xrLCAqcGl4 X2NsazsKPiArCj4gKwl1MzIgbGNkX21vZGU7Cj4gKwo+ICsJc3RydWN0IGluZ2VuaWNfZG1hX2h3 ZGVzYyAqZG1hX2h3ZGVzYzsKPiArCWRtYV9hZGRyX3QgZG1hX2h3ZGVzY19waHlzOwo+ICt9Owo+ ICsKPiArc3RhdGljIGNvbnN0IHUzMiBpbmdlbmljX2RybV9wcmltYXJ5X2Zvcm1hdHNbXSA9IHsK PiArCURSTV9GT1JNQVRfWFJHQjE1NTUsCj4gKwlEUk1fRk9STUFUX1JHQjU2NSwKPiArCURSTV9G T1JNQVRfWFJHQjg4ODgsCj4gK307Cj4gKwo+ICtzdGF0aWMgYm9vbCBpbmdlbmljX2RybV93cml0 ZWFibGVfcmVnKHN0cnVjdCBkZXZpY2UgKmRldiwgdW5zaWduZWQgaW50IHJlZykKPiArewo+ICsJ c3dpdGNoIChyZWcpIHsKPiArCWNhc2UgSlpfUkVHX0xDRF9JSUQ6Cj4gKwljYXNlIEpaX1JFR19M Q0RfU0EwOgo+ICsJY2FzZSBKWl9SRUdfTENEX0ZJRDA6Cj4gKwljYXNlIEpaX1JFR19MQ0RfQ01E MDoKPiArCWNhc2UgSlpfUkVHX0xDRF9TQTE6Cj4gKwljYXNlIEpaX1JFR19MQ0RfRklEMToKPiAr CWNhc2UgSlpfUkVHX0xDRF9DTUQxOgo+ICsJCXJldHVybiBmYWxzZTsKPiArCWRlZmF1bHQ6Cj4g KwkJcmV0dXJuIHRydWU7Cj4gKwl9Cj4gK30KPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgcmVn bWFwX2NvbmZpZyBpbmdlbmljX2RybV9yZWdtYXBfY29uZmlnID0gewo+ICsJLnJlZ19iaXRzID0g MzIsCj4gKwkudmFsX2JpdHMgPSAzMiwKPiArCS5yZWdfc3RyaWRlID0gNCwKPiArCj4gKwkubWF4 X3JlZ2lzdGVyID0gSlpfUkVHX0xDRF9DTUQxLAo+ICsJLndyaXRlYWJsZV9yZWcgPSBpbmdlbmlj X2RybV93cml0ZWFibGVfcmVnLAo+ICt9Owo+ICsKPiArc3RhdGljIGlubGluZSBzdHJ1Y3QgaW5n ZW5pY19kcm0gKmRybV9kZXZpY2VfZ2V0X3ByaXYoc3RydWN0IGRybV9kZXZpY2UgKmRybSkKPiAr ewo+ICsJcmV0dXJuIGNvbnRhaW5lcl9vZihkcm0sIHN0cnVjdCBpbmdlbmljX2RybSwgZHJtKTsK PiArfQo+ICsKPiArc3RhdGljIGlubGluZSBzdHJ1Y3QgaW5nZW5pY19kcm0gKmRybV9jcnRjX2dl dF9wcml2KHN0cnVjdCBkcm1fY3J0YyAqY3J0YykKPiArewo+ICsJcmV0dXJuIGNvbnRhaW5lcl9v ZihjcnRjLCBzdHJ1Y3QgaW5nZW5pY19kcm0sIGNydGMpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW5s aW5lIHN0cnVjdCBpbmdlbmljX2RybSAqCj4gK2RybV9lbmNvZGVyX2dldF9wcml2KHN0cnVjdCBk cm1fZW5jb2RlciAqZW5jb2RlcikKPiArewo+ICsJcmV0dXJuIGNvbnRhaW5lcl9vZihlbmNvZGVy LCBzdHJ1Y3QgaW5nZW5pY19kcm0sIGVuY29kZXIpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW5saW5l IHN0cnVjdCBpbmdlbmljX2RybSAqZHJtX3BsYW5lX2dldF9wcml2KHN0cnVjdCBkcm1fcGxhbmUg KnBsYW5lKQo+ICt7Cj4gKwlyZXR1cm4gY29udGFpbmVyX29mKHBsYW5lLCBzdHJ1Y3QgaW5nZW5p Y19kcm0sIHByaW1hcnkpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBpbmdlbmljX2RybV9jcnRj X2F0b21pY19lbmFibGUoc3RydWN0IGRybV9jcnRjICpjcnRjLAo+ICsJCQkJCSAgc3RydWN0IGRy bV9jcnRjX3N0YXRlICpzdGF0ZSkKPiArewo+ICsJc3RydWN0IGluZ2VuaWNfZHJtICpwcml2ID0g ZHJtX2NydGNfZ2V0X3ByaXYoY3J0Yyk7Cj4gKwo+ICsJcmVnbWFwX3dyaXRlKHByaXYtPm1hcCwg SlpfUkVHX0xDRF9TVEFURSwgMCk7Cj4gKwo+ICsJcmVnbWFwX3VwZGF0ZV9iaXRzKHByaXYtPm1h cCwgSlpfUkVHX0xDRF9DVFJMLAo+ICsJCQkgICBKWl9MQ0RfQ1RSTF9FTkFCTEUgfCBKWl9MQ0Rf Q1RSTF9ESVNBQkxFLAo+ICsJCQkgICBKWl9MQ0RfQ1RSTF9FTkFCTEUpOwo+ICsKPiArCWRybV9j cnRjX3ZibGFua19vbihjcnRjKTsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQgaW5nZW5pY19kcm1f Y3J0Y19hdG9taWNfZGlzYWJsZShzdHJ1Y3QgZHJtX2NydGMgKmNydGMsCj4gKwkJCQkJICAgc3Ry dWN0IGRybV9jcnRjX3N0YXRlICpzdGF0ZSkKPiArewo+ICsJc3RydWN0IGluZ2VuaWNfZHJtICpw cml2ID0gZHJtX2NydGNfZ2V0X3ByaXYoY3J0Yyk7Cj4gKwl1bnNpZ25lZCBpbnQgdmFyOwo+ICsK PiArCWRybV9jcnRjX3ZibGFua19vZmYoY3J0Yyk7Cj4gKwo+ICsJcmVnbWFwX3VwZGF0ZV9iaXRz KHByaXYtPm1hcCwgSlpfUkVHX0xDRF9DVFJMLAo+ICsJCQkgICBKWl9MQ0RfQ1RSTF9ESVNBQkxF LCBKWl9MQ0RfQ1RSTF9ESVNBQkxFKTsKPiArCj4gKwlyZWdtYXBfcmVhZF9wb2xsX3RpbWVvdXQo cHJpdi0+bWFwLCBKWl9SRUdfTENEX1NUQVRFLCB2YXIsCj4gKwkJCQkgdmFyICYgSlpfTENEX1NU QVRFX0RJU0FCTEVELAo+ICsJCQkJIDEwMDAsIDApOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW5saW5l IGJvb2wgaW5nZW5pY19kcm1fbGNkX2lzX3NwZWNpYWxfbW9kZSh1MzIgbW9kZSkKPiArewo+ICsJ c3dpdGNoIChtb2RlKSB7Cj4gKwljYXNlIEpaX0xDRF9TUEVDSUFMX1RGVF8xOgo+ICsJY2FzZSBK Wl9MQ0RfU1BFQ0lBTF9URlRfMjoKPiArCWNhc2UgSlpfTENEX1NQRUNJQUxfVEZUXzM6Cj4gKwkJ cmV0dXJuIHRydWU7Cj4gKwlkZWZhdWx0Ogo+ICsJCXJldHVybiBmYWxzZTsKPiArCX0KPiArfQo+ ICsKPiArc3RhdGljIHZvaWQgaW5nZW5pY19kcm1fY3J0Y191cGRhdGVfdGltaW5ncyhzdHJ1Y3Qg aW5nZW5pY19kcm0gKnByaXYsCj4gKwkJCQkJICAgIHN0cnVjdCBkcm1fZGlzcGxheV9tb2RlICpt b2RlKQo+ICt7Cj4gKwl1bnNpZ25lZCBpbnQgdnBlLCB2ZHMsIHZkZSwgdnQsIGhwZSwgaGRzLCBo ZGUsIGh0Owo+ICsKPiArCXZwZSA9IG1vZGUtPnZzeW5jX2VuZCAtIG1vZGUtPnZzeW5jX3N0YXJ0 Owo+ICsJdmRzID0gbW9kZS0+dnRvdGFsIC0gbW9kZS0+dnN5bmNfc3RhcnQ7Cj4gKwl2ZGUgPSB2 ZHMgKyBtb2RlLT52ZGlzcGxheTsKPiArCXZ0ID0gdmRlICsgbW9kZS0+dnN5bmNfc3RhcnQgLSBt b2RlLT52ZGlzcGxheTsKPiArCj4gKwlocGUgPSBtb2RlLT5oc3luY19lbmQgLSBtb2RlLT5oc3lu Y19zdGFydDsKPiArCWhkcyA9IG1vZGUtPmh0b3RhbCAtIG1vZGUtPmhzeW5jX3N0YXJ0Owo+ICsJ aGRlID0gaGRzICsgbW9kZS0+aGRpc3BsYXk7Cj4gKwlodCA9IGhkZSArIG1vZGUtPmhzeW5jX3N0 YXJ0IC0gbW9kZS0+aGRpc3BsYXk7Cj4gKwo+ICsJcmVnbWFwX3dyaXRlKHByaXYtPm1hcCwgSlpf UkVHX0xDRF9WU1lOQywKPiArCQkgICAgIDAgPDwgSlpfTENEX1ZTWU5DX1ZQU19PRkZTRVQgfAo+ ICsJCSAgICAgdnBlIDw8IEpaX0xDRF9WU1lOQ19WUEVfT0ZGU0VUKTsKPiArCj4gKwlyZWdtYXBf d3JpdGUocHJpdi0+bWFwLCBKWl9SRUdfTENEX0hTWU5DLAo+ICsJCSAgICAgMCA8PCBKWl9MQ0Rf SFNZTkNfSFBTX09GRlNFVCB8Cj4gKwkJICAgICBocGUgPDwgSlpfTENEX0hTWU5DX0hQRV9PRkZT RVQpOwo+ICsKPiArCXJlZ21hcF93cml0ZShwcml2LT5tYXAsIEpaX1JFR19MQ0RfVkFULAo+ICsJ CSAgICAgaHQgPDwgSlpfTENEX1ZBVF9IVF9PRkZTRVQgfAo+ICsJCSAgICAgdnQgPDwgSlpfTENE X1ZBVF9WVF9PRkZTRVQpOwo+ICsKPiArCXJlZ21hcF93cml0ZShwcml2LT5tYXAsIEpaX1JFR19M Q0RfREFILAo+ICsJCSAgICAgaGRzIDw8IEpaX0xDRF9EQUhfSERTX09GRlNFVCB8Cj4gKwkJICAg ICBoZGUgPDwgSlpfTENEX0RBSF9IREVfT0ZGU0VUKTsKPiArCXJlZ21hcF93cml0ZShwcml2LT5t YXAsIEpaX1JFR19MQ0RfREFWLAo+ICsJCSAgICAgdmRzIDw8IEpaX0xDRF9EQVZfVkRTX09GRlNF VCB8Cj4gKwkJICAgICB2ZGUgPDwgSlpfTENEX0RBVl9WREVfT0ZGU0VUKTsKPiArCj4gKwlpZiAo aW5nZW5pY19kcm1fbGNkX2lzX3NwZWNpYWxfbW9kZShwcml2LT5sY2RfbW9kZSkpIHsKPiArCQly ZWdtYXBfd3JpdGUocHJpdi0+bWFwLCBKWl9SRUdfTENEX1BTLCBoZGUgPDwgMTYgfCAoaGRlICsg MSkpOwo+ICsJCXJlZ21hcF93cml0ZShwcml2LT5tYXAsIEpaX1JFR19MQ0RfQ0xTLCBoZGUgPDwg MTYgfCAoaGRlICsgMSkpOwo+ICsJCXJlZ21hcF93cml0ZShwcml2LT5tYXAsIEpaX1JFR19MQ0Rf U1BMLCBocGUgPDwgMTYgfCAoaHBlICsgMSkpOwo+ICsJCXJlZ21hcF93cml0ZShwcml2LT5tYXAs IEpaX1JFR19MQ0RfUkVWLCBtb2RlLT5odG90YWwgPDwgMTYpOwo+ICsJfQo+ICt9Cj4gKwo+ICtz dGF0aWMgdm9pZCBpbmdlbmljX2RybV9jcnRjX3VwZGF0ZV9jdHJsKHN0cnVjdCBpbmdlbmljX2Ry bSAqcHJpdiwKPiArCQkJCQkgdW5zaWduZWQgaW50IGJwcCkKPiArewo+ICsJdW5zaWduZWQgaW50 IGN0cmwgPSBKWl9MQ0RfQ1RSTF9PRlVQIHwgSlpfTENEX0NUUkxfQlVSU1RfMTY7Cj4gKwo+ICsJ c3dpdGNoIChicHApIHsKPiArCWNhc2UgMToKPiArCQljdHJsIHw9IEpaX0xDRF9DVFJMX0JQUF8x Owo+ICsJCWJyZWFrOwo+ICsJY2FzZSAyOgo+ICsJCWN0cmwgfD0gSlpfTENEX0NUUkxfQlBQXzI7 Cj4gKwkJYnJlYWs7Cj4gKwljYXNlIDQ6Cj4gKwkJY3RybCB8PSBKWl9MQ0RfQ1RSTF9CUFBfNDsK PiArCQlicmVhazsKPiArCWNhc2UgODoKPiArCQljdHJsIHw9IEpaX0xDRF9DVFJMX0JQUF84Owo+ ICsJYnJlYWs7Cj4gKwljYXNlIDE1Ogo+ICsJCWN0cmwgfD0gSlpfTENEX0NUUkxfUkdCNTU1OyAv KiBGYWxsdHJvdWdoICovCj4gKwljYXNlIDE2Ogo+ICsJCWN0cmwgfD0gSlpfTENEX0NUUkxfQlBQ XzE1XzE2Owo+ICsJCWJyZWFrOwo+ICsJY2FzZSAxODoKPiArCWNhc2UgMjQ6Cj4gKwljYXNlIDMy Ogo+ICsJCWN0cmwgfD0gSlpfTENEX0NUUkxfQlBQXzE4XzI0Owo+ICsJCWJyZWFrOwo+ICsJZGVm YXVsdDoKPiArCQlicmVhazsKPiArCX0KPiArCj4gKwlyZWdtYXBfdXBkYXRlX2JpdHMocHJpdi0+ bWFwLCBKWl9SRUdfTENEX0NUUkwsCj4gKwkJCSAgIEpaX0xDRF9DVFJMX09GVVAgfCBKWl9MQ0Rf Q1RSTF9CVVJTVF8xNiB8Cj4gKwkJCSAgIEpaX0xDRF9DVFJMX0JQUF9NQVNLLCBjdHJsKTsKPiAr fQo+ICsKPiArc3RhdGljIGludCBpbmdlbmljX2RybV9jcnRjX2F0b21pY19jaGVjayhzdHJ1Y3Qg ZHJtX2NydGMgKmNydGMsCj4gKwkJCQkJIHN0cnVjdCBkcm1fY3J0Y19zdGF0ZSAqc3RhdGUpCj4g K3sKPiArCXN0cnVjdCBpbmdlbmljX2RybSAqcHJpdiA9IGRybV9jcnRjX2dldF9wcml2KGNydGMp Owo+ICsJbG9uZyByYXRlOwo+ICsKPiArCWlmICghZHJtX2F0b21pY19jcnRjX25lZWRzX21vZGVz ZXQoc3RhdGUpKQo+ICsJCXJldHVybiAwOwo+ICsKPiArCXJhdGUgPSBjbGtfcm91bmRfcmF0ZShw cml2LT5waXhfY2xrLAo+ICsJCQkgICAgICBzdGF0ZS0+YWRqdXN0ZWRfbW9kZS5jbG9jayAqIDEw MDApOwo+ICsJaWYgKHJhdGUgPCAwKQo+ICsJCXJldHVybiByYXRlOwo+ICsKPiArCXJldHVybiAw Owo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBpbmdlbmljX2RybV9jcnRjX2F0b21pY19mbHVzaChz dHJ1Y3QgZHJtX2NydGMgKmNydGMsCj4gKwkJCQkJICBzdHJ1Y3QgZHJtX2NydGNfc3RhdGUgKm9s ZHN0YXRlKQo+ICt7Cj4gKwlzdHJ1Y3QgaW5nZW5pY19kcm0gKnByaXYgPSBkcm1fY3J0Y19nZXRf cHJpdihjcnRjKTsKPiArCXN0cnVjdCBkcm1fY3J0Y19zdGF0ZSAqc3RhdGUgPSBjcnRjLT5zdGF0 ZTsKPiArCXN0cnVjdCBkcm1fcGVuZGluZ192YmxhbmtfZXZlbnQgKmV2ZW50ID0gc3RhdGUtPmV2 ZW50Owo+ICsJc3RydWN0IGRybV9mcmFtZWJ1ZmZlciAqZHJtX2ZiID0gY3J0Yy0+cHJpbWFyeS0+ c3RhdGUtPmZiOwo+ICsJY29uc3Qgc3RydWN0IGRybV9mb3JtYXRfaW5mbyAqZmluZm87Cj4gKwo+ ICsJaWYgKGRybV9hdG9taWNfY3J0Y19uZWVkc19tb2Rlc2V0KHN0YXRlKSkgewo+ICsJCWZpbmZv ID0gZHJtX2Zvcm1hdF9pbmZvKGRybV9mYi0+Zm9ybWF0LT5mb3JtYXQpOwo+ICsKPiArCQlpbmdl bmljX2RybV9jcnRjX3VwZGF0ZV90aW1pbmdzKHByaXYsICZzdGF0ZS0+bW9kZSk7Cj4gKwkJaW5n ZW5pY19kcm1fY3J0Y191cGRhdGVfY3RybChwcml2LCBmaW5mby0+ZGVwdGgpOwo+ICsKPiArCQlj bGtfc2V0X3JhdGUocHJpdi0+cGl4X2Nsaywgc3RhdGUtPmFkanVzdGVkX21vZGUuY2xvY2sgKiAx MDAwKTsKPiArCj4gKwkJcmVnbWFwX3dyaXRlKHByaXYtPm1hcCwgSlpfUkVHX0xDRF9EQTAsIHBy aXYtPmRtYV9od2Rlc2MtPm5leHQpOwo+ICsJfQo+ICsKPiArCWlmIChldmVudCkgewo+ICsJCXN0 YXRlLT5ldmVudCA9IE5VTEw7Cj4gKwo+ICsJCXNwaW5fbG9ja19pcnEoJmNydGMtPmRldi0+ZXZl bnRfbG9jayk7Cj4gKwkJaWYgKGRybV9jcnRjX3ZibGFua19nZXQoY3J0YykgPT0gMCkKPiArCQkJ ZHJtX2NydGNfYXJtX3ZibGFua19ldmVudChjcnRjLCBldmVudCk7Cj4gKwkJZWxzZQo+ICsJCQlk cm1fY3J0Y19zZW5kX3ZibGFua19ldmVudChjcnRjLCBldmVudCk7Cj4gKwkJc3Bpbl91bmxvY2tf aXJxKCZjcnRjLT5kZXYtPmV2ZW50X2xvY2spOwo+ICsJfQo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9p ZCBpbmdlbmljX2RybV9wbGFuZV9hdG9taWNfdXBkYXRlKHN0cnVjdCBkcm1fcGxhbmUgKnBsYW5l LAo+ICsJCQkJCSAgICBzdHJ1Y3QgZHJtX3BsYW5lX3N0YXRlICpvbGRzdGF0ZSkKPiArewo+ICsJ c3RydWN0IGluZ2VuaWNfZHJtICpwcml2ID0gZHJtX3BsYW5lX2dldF9wcml2KHBsYW5lKTsKPiAr CXN0cnVjdCBkcm1fcGxhbmVfc3RhdGUgKnN0YXRlID0gcGxhbmUtPnN0YXRlOwo+ICsJY29uc3Qg c3RydWN0IGRybV9mb3JtYXRfaW5mbyAqZmluZm87Cj4gKwl1bnNpZ25lZCBpbnQgd2lkdGgsIGhl aWdodDsKPiArCj4gKwlmaW5mbyA9IGRybV9mb3JtYXRfaW5mbyhzdGF0ZS0+ZmItPmZvcm1hdC0+ Zm9ybWF0KTsKPiArCXdpZHRoID0gc3RhdGUtPmNydGMtPnN0YXRlLT5hZGp1c3RlZF9tb2RlLmhk aXNwbGF5Owo+ICsJaGVpZ2h0ID0gc3RhdGUtPmNydGMtPnN0YXRlLT5hZGp1c3RlZF9tb2RlLnZk aXNwbGF5Owo+ICsKPiArCXByaXYtPmRtYV9od2Rlc2MtPmFkZHIgPSBkcm1fZmJfY21hX2dldF9n ZW1fYWRkcihzdGF0ZS0+ZmIsIHN0YXRlLCAwKTsKPiArCj4gKwlwcml2LT5kbWFfaHdkZXNjLT5j bWQgPSB3aWR0aCAqIGhlaWdodCAqICgoZmluZm8tPmRlcHRoICsgNykgLyA4KSAvIDQ7Cj4gKwlw cml2LT5kbWFfaHdkZXNjLT5jbWQgfD0gSlpfTENEX0NNRF9FT0ZfSVJROwo+ICt9Cj4gKwo+ICtz dGF0aWMgdm9pZCBpbmdlbmljX2RybV9lbmNvZGVyX2F0b21pY19tb2RlX3NldChzdHJ1Y3QgZHJt X2VuY29kZXIgKmVuY29kZXIsCj4gKwkJCQkJCXN0cnVjdCBkcm1fY3J0Y19zdGF0ZSAqY3J0Y19z dGF0ZSwKPiArCQkJCQkJc3RydWN0IGRybV9jb25uZWN0b3Jfc3RhdGUgKmNvbm5fc3RhdGUpCj4g K3sKPiArCXN0cnVjdCBpbmdlbmljX2RybSAqcHJpdiA9IGRybV9lbmNvZGVyX2dldF9wcml2KGVu Y29kZXIpOwo+ICsJc3RydWN0IGRybV9kaXNwbGF5X21vZGUgKm1vZGUgPSAmY3J0Y19zdGF0ZS0+ YWRqdXN0ZWRfbW9kZTsKPiArCXUzMiBidXNfZmxhZ3MgPSBjb25uX3N0YXRlLT5jb25uZWN0b3It PmRpc3BsYXlfaW5mby5idXNfZmxhZ3M7Cj4gKwl1bnNpZ25lZCBpbnQgY2ZnID0gcHJpdi0+bGNk X21vZGU7Cj4gKwo+ICsJaWYgKG1vZGUtPmZsYWdzICYgRFJNX01PREVfRkxBR19OSFNZTkMpCj4g KwkJY2ZnIHw9IEpaX0xDRF9DRkdfSFNZTkNfQUNUSVZFX0xPVzsKPiArCWlmIChtb2RlLT5mbGFn cyAmIERSTV9NT0RFX0ZMQUdfTlZTWU5DKQo+ICsJCWNmZyB8PSBKWl9MQ0RfQ0ZHX1ZTWU5DX0FD VElWRV9MT1c7Cj4gKwlpZiAoYnVzX2ZsYWdzICYgRFJNX0JVU19GTEFHX0RFX0xPVykKPiArCQlj ZmcgfD0gSlpfTENEX0NGR19ERV9BQ1RJVkVfTE9XOwo+ICsJaWYgKGJ1c19mbGFncyAmIERSTV9C VVNfRkxBR19QSVhEQVRBX05FR0VER0UpCj4gKwkJY2ZnIHw9IEpaX0xDRF9DRkdfUENMS19GQUxM SU5HX0VER0U7Cj4gKwo+ICsJaWYgKGluZ2VuaWNfZHJtX2xjZF9pc19zcGVjaWFsX21vZGUocHJp di0+bGNkX21vZGUpKSB7Cj4gKwkJLyogVE9ETzogSXMgdGhhdCB2YWxpZCBmb3IgYWxsIHNwZWNp YWwgbW9kZXM/ICovCj4gKwkJY2ZnIHw9IEpaX0xDRF9DRkdfUkVWX1BPTEFSSVRZOwo+ICsJfSBl bHNlIHsKPiArCQljZmcgfD0gSlpfTENEX0NGR19QU19ESVNBQkxFCj4gKwkJICAgIHwgSlpfTENE X0NGR19DTFNfRElTQUJMRQo+ICsJCSAgICB8IEpaX0xDRF9DRkdfU1BMX0RJU0FCTEUKPiArCQkg ICAgfCBKWl9MQ0RfQ0ZHX1JFVl9ESVNBQkxFOwo+ICsJfQo+ICsKPiArCXJlZ21hcF93cml0ZShw cml2LT5tYXAsIEpaX1JFR19MQ0RfQ0ZHLCBjZmcpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaXJxcmV0 dXJuX3QgaW5nZW5pY19kcm1faXJxX2hhbmRsZXIoaW50IGlycSwgdm9pZCAqYXJnKQo+ICt7Cj4g KwlzdHJ1Y3QgaW5nZW5pY19kcm0gKnByaXYgPSBhcmc7Cj4gKwl1bnNpZ25lZCBpbnQgc3RhdGU7 Cj4gKwo+ICsJcmVnbWFwX3JlYWQocHJpdi0+bWFwLCBKWl9SRUdfTENEX1NUQVRFLCAmc3RhdGUp Owo+ICsKPiArCXJlZ21hcF91cGRhdGVfYml0cyhwcml2LT5tYXAsIEpaX1JFR19MQ0RfU1RBVEUs Cj4gKwkJCSAgIEpaX0xDRF9TVEFURV9FT0ZfSVJRLCAwKTsKPiArCj4gKwlpZiAoc3RhdGUgJiBK Wl9MQ0RfU1RBVEVfRU9GX0lSUSkKPiArCQlkcm1fY3J0Y19oYW5kbGVfdmJsYW5rKCZwcml2LT5j cnRjKTsKPiArCj4gKwlyZXR1cm4gSVJRX0hBTkRMRUQ7Cj4gK30KPiArCj4gK3N0YXRpYyB2b2lk IGluZ2VuaWNfZHJtX3JlbGVhc2Uoc3RydWN0IGRybV9kZXZpY2UgKmRybSkKPiArewo+ICsJc3Ry dWN0IGluZ2VuaWNfZHJtICpwcml2ID0gZHJtX2RldmljZV9nZXRfcHJpdihkcm0pOwo+ICsKPiAr CWRybV9tb2RlX2NvbmZpZ19jbGVhbnVwKGRybSk7Cj4gKwlkcm1fZGV2X2ZpbmkoZHJtKTsKPiAr CWtmcmVlKHByaXYpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50IGluZ2VuaWNfZHJtX2VuYWJsZV92 Ymxhbmsoc3RydWN0IGRybV9jcnRjICpjcnRjKQo+ICt7Cj4gKwlzdHJ1Y3QgaW5nZW5pY19kcm0g KnByaXYgPSBkcm1fY3J0Y19nZXRfcHJpdihjcnRjKTsKPiArCj4gKwlyZWdtYXBfdXBkYXRlX2Jp dHMocHJpdi0+bWFwLCBKWl9SRUdfTENEX0NUUkwsCj4gKwkJCSAgIEpaX0xDRF9DVFJMX0VPRl9J UlEsIEpaX0xDRF9DVFJMX0VPRl9JUlEpOwo+ICsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICtz dGF0aWMgdm9pZCBpbmdlbmljX2RybV9kaXNhYmxlX3ZibGFuayhzdHJ1Y3QgZHJtX2NydGMgKmNy dGMpCj4gK3sKPiArCXN0cnVjdCBpbmdlbmljX2RybSAqcHJpdiA9IGRybV9jcnRjX2dldF9wcml2 KGNydGMpOwo+ICsKPiArCXJlZ21hcF91cGRhdGVfYml0cyhwcml2LT5tYXAsIEpaX1JFR19MQ0Rf Q1RSTCwgSlpfTENEX0NUUkxfRU9GX0lSUSwgMCk7Cj4gK30KPiArCj4gK0RFRklORV9EUk1fR0VN X0NNQV9GT1BTKGluZ2VuaWNfZHJtX2ZvcHMpOwo+ICsKPiArc3RhdGljIHN0cnVjdCBkcm1fZHJp dmVyIGluZ2VuaWNfZHJtX2RyaXZlcl9kYXRhID0gewo+ICsJLmRyaXZlcl9mZWF0dXJlcwk9IERS SVZFUl9NT0RFU0VUIHwgRFJJVkVSX0dFTSB8IERSSVZFUl9QUklNRQo+ICsJCQkJfCBEUklWRVJf QVRPTUlDLAo+ICsJLm5hbWUJCQk9ICJpbmdlbmljLWRybSIsCj4gKwkuZGVzYwkJCT0gIkRSTSBt b2R1bGUgZm9yIEluZ2VuaWMgU29DcyIsCj4gKwkuZGF0ZQkJCT0gIjIwMTkwMjI4IiwKPiArCS5t YWpvcgkJCT0gMSwKPiArCS5taW5vcgkJCT0gMCwKPiArCS5wYXRjaGxldmVsCQk9IDAsCj4gKwo+ ICsJLmZvcHMJCQk9ICZpbmdlbmljX2RybV9mb3BzLAo+ICsKPiArCS5kdW1iX2NyZWF0ZQkJPSBk cm1fZ2VtX2NtYV9kdW1iX2NyZWF0ZSwKPiArCS5nZW1fZnJlZV9vYmplY3RfdW5sb2NrZWQgPSBk cm1fZ2VtX2NtYV9mcmVlX29iamVjdCwKPiArCS5nZW1fdm1fb3BzCQk9ICZkcm1fZ2VtX2NtYV92 bV9vcHMsCj4gKwo+ICsJLnByaW1lX2hhbmRsZV90b19mZAk9IGRybV9nZW1fcHJpbWVfaGFuZGxl X3RvX2ZkLAo+ICsJLnByaW1lX2ZkX3RvX2hhbmRsZQk9IGRybV9nZW1fcHJpbWVfZmRfdG9faGFu ZGxlLAo+ICsJLmdlbV9wcmltZV9nZXRfc2dfdGFibGUJPSBkcm1fZ2VtX2NtYV9wcmltZV9nZXRf c2dfdGFibGUsCj4gKwkuZ2VtX3ByaW1lX2ltcG9ydF9zZ190YWJsZSA9IGRybV9nZW1fY21hX3By aW1lX2ltcG9ydF9zZ190YWJsZSwKPiArCS5nZW1fcHJpbWVfdm1hcAkJPSBkcm1fZ2VtX2NtYV9w cmltZV92bWFwLAo+ICsJLmdlbV9wcmltZV92dW5tYXAJPSBkcm1fZ2VtX2NtYV9wcmltZV92dW5t YXAsCj4gKwkuZ2VtX3ByaW1lX21tYXAJCT0gZHJtX2dlbV9jbWFfcHJpbWVfbW1hcCwKPiArCj4g KwkuaXJxX2hhbmRsZXIJCT0gaW5nZW5pY19kcm1faXJxX2hhbmRsZXIsCj4gKwkucmVsZWFzZQkJ CT0gaW5nZW5pY19kcm1fcmVsZWFzZSwKPiArfTsKPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg ZHJtX3BsYW5lX2Z1bmNzIGluZ2VuaWNfZHJtX3ByaW1hcnlfcGxhbmVfZnVuY3MgPSB7Cj4gKwku dXBkYXRlX3BsYW5lCQk9IGRybV9hdG9taWNfaGVscGVyX3VwZGF0ZV9wbGFuZSwKPiArCS5kaXNh YmxlX3BsYW5lCQk9IGRybV9hdG9taWNfaGVscGVyX2Rpc2FibGVfcGxhbmUsCj4gKwkucmVzZXQJ CQk9IGRybV9hdG9taWNfaGVscGVyX3BsYW5lX3Jlc2V0LAo+ICsJLmRlc3Ryb3kJCT0gZHJtX3Bs YW5lX2NsZWFudXAsCj4gKwo+ICsJLmF0b21pY19kdXBsaWNhdGVfc3RhdGUJPSBkcm1fYXRvbWlj X2hlbHBlcl9wbGFuZV9kdXBsaWNhdGVfc3RhdGUsCj4gKwkuYXRvbWljX2Rlc3Ryb3lfc3RhdGUJ PSBkcm1fYXRvbWljX2hlbHBlcl9wbGFuZV9kZXN0cm95X3N0YXRlLAo+ICt9Owo+ICsKPiArc3Rh dGljIGNvbnN0IHN0cnVjdCBkcm1fY3J0Y19mdW5jcyBpbmdlbmljX2RybV9jcnRjX2Z1bmNzID0g ewo+ICsJLnNldF9jb25maWcJCT0gZHJtX2F0b21pY19oZWxwZXJfc2V0X2NvbmZpZywKPiArCS5w YWdlX2ZsaXAJCT0gZHJtX2F0b21pY19oZWxwZXJfcGFnZV9mbGlwLAo+ICsJLnJlc2V0CQkJPSBk cm1fYXRvbWljX2hlbHBlcl9jcnRjX3Jlc2V0LAo+ICsJLmRlc3Ryb3kJCT0gZHJtX2NydGNfY2xl YW51cCwKPiArCj4gKwkuYXRvbWljX2R1cGxpY2F0ZV9zdGF0ZQk9IGRybV9hdG9taWNfaGVscGVy X2NydGNfZHVwbGljYXRlX3N0YXRlLAo+ICsJLmF0b21pY19kZXN0cm95X3N0YXRlCT0gZHJtX2F0 b21pY19oZWxwZXJfY3J0Y19kZXN0cm95X3N0YXRlLAo+ICsKPiArCS5lbmFibGVfdmJsYW5rCQk9 IGluZ2VuaWNfZHJtX2VuYWJsZV92YmxhbmssCj4gKwkuZGlzYWJsZV92YmxhbmsJCT0gaW5nZW5p Y19kcm1fZGlzYWJsZV92YmxhbmssCj4gKwo+ICsJLmdhbW1hX3NldAkJPSBkcm1fYXRvbWljX2hl bHBlcl9sZWdhY3lfZ2FtbWFfc2V0LAo+ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVjdCBk cm1fcGxhbmVfaGVscGVyX2Z1bmNzIGluZ2VuaWNfZHJtX3BsYW5lX2hlbHBlcl9mdW5jcyA9IHsK PiArCS5hdG9taWNfdXBkYXRlCQk9IGluZ2VuaWNfZHJtX3BsYW5lX2F0b21pY191cGRhdGUsCj4g KwkucHJlcGFyZV9mYgkJPSBkcm1fZ2VtX2ZiX3ByZXBhcmVfZmIsCj4gK307Cj4gKwo+ICtzdGF0 aWMgY29uc3Qgc3RydWN0IGRybV9jcnRjX2hlbHBlcl9mdW5jcyBpbmdlbmljX2RybV9jcnRjX2hl bHBlcl9mdW5jcyA9IHsKPiArCS5hdG9taWNfZW5hYmxlCQk9IGluZ2VuaWNfZHJtX2NydGNfYXRv bWljX2VuYWJsZSwKPiArCS5hdG9taWNfZGlzYWJsZQkJPSBpbmdlbmljX2RybV9jcnRjX2F0b21p Y19kaXNhYmxlLAo+ICsJLmF0b21pY19mbHVzaAkJPSBpbmdlbmljX2RybV9jcnRjX2F0b21pY19m bHVzaCwKPiArCS5hdG9taWNfY2hlY2sJCT0gaW5nZW5pY19kcm1fY3J0Y19hdG9taWNfY2hlY2ss Cj4gK307Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9lbmNvZGVyX2hlbHBlcl9mdW5j cyBpbmdlbmljX2RybV9lbmNvZGVyX2hlbHBlcl9mdW5jcyA9IHsKPiArCS5hdG9taWNfbW9kZV9z ZXQJPSBpbmdlbmljX2RybV9lbmNvZGVyX2F0b21pY19tb2RlX3NldCwKPiArfTsKPiArCj4gK3N0 YXRpYyBjb25zdCBzdHJ1Y3QgZHJtX21vZGVfY29uZmlnX2Z1bmNzIGluZ2VuaWNfZHJtX21vZGVf Y29uZmlnX2Z1bmNzID0gewo+ICsJLmZiX2NyZWF0ZQkJPSBkcm1fZ2VtX2ZiX2NyZWF0ZSwKPiAr CS5vdXRwdXRfcG9sbF9jaGFuZ2VkCT0gZHJtX2ZiX2hlbHBlcl9vdXRwdXRfcG9sbF9jaGFuZ2Vk LAo+ICsJLmF0b21pY19jaGVjawkJPSBkcm1fYXRvbWljX2hlbHBlcl9jaGVjaywKPiArCS5hdG9t aWNfY29tbWl0CQk9IGRybV9hdG9taWNfaGVscGVyX2NvbW1pdCwKPiArfTsKPiArCj4gK3N0YXRp YyBjb25zdCBzdHJ1Y3QgZHJtX2VuY29kZXJfZnVuY3MgaW5nZW5pY19kcm1fZW5jb2Rlcl9mdW5j cyA9IHsKPiArCS5kZXN0cm95CQk9IGRybV9lbmNvZGVyX2NsZWFudXAsCj4gK307Cj4gKwo+ICtz dGF0aWMgdm9pZCBpbmdlbmljX2RybV9mcmVlX2RtYV9od2Rlc2Modm9pZCAqZCkKPiArewo+ICsJ c3RydWN0IGluZ2VuaWNfZHJtICpwcml2ID0gZDsKPiArCj4gKwlkbWFfZnJlZV9jb2hlcmVudChw cml2LT5kZXYsIHNpemVvZigqcHJpdi0+ZG1hX2h3ZGVzYyksCj4gKwkJCSAgcHJpdi0+ZG1hX2h3 ZGVzYywgcHJpdi0+ZG1hX2h3ZGVzY19waHlzKTsKPiArfQo+ICsKPiArc3RhdGljIGludCBpbmdl bmljX2RybV9wcm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQo+ICt7Cj4gKwljb25z dCBzdHJ1Y3Qganpfc29jX2luZm8gKnNvY19pbmZvOwo+ICsJc3RydWN0IGRldmljZSAqZGV2ID0g JnBkZXYtPmRldjsKPiArCXN0cnVjdCBpbmdlbmljX2RybSAqcHJpdjsKPiArCXN0cnVjdCBjbGsg KnBhcmVudF9jbGs7Cj4gKwlzdHJ1Y3QgZHJtX2JyaWRnZSAqYnJpZGdlOwo+ICsJc3RydWN0IGRy bV9wYW5lbCAqcGFuZWw7Cj4gKwlzdHJ1Y3QgZHJtX2RldmljZSAqZHJtOwo+ICsJc3RydWN0IHJl c291cmNlICptZW07Cj4gKwl2b2lkIF9faW9tZW0gKmJhc2U7Cj4gKwlsb25nIHBhcmVudF9yYXRl Owo+ICsJaW50IHJldCwgaXJxOwo+ICsKPiArCXNvY19pbmZvID0gb2ZfZGV2aWNlX2dldF9tYXRj aF9kYXRhKGRldik7Cj4gKwlpZiAoIXNvY19pbmZvKSB7Cj4gKwkJZGV2X2VycihkZXYsICJNaXNz aW5nIHBsYXRmb3JtIGRhdGFcbiIpOwo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsJfQo+ICsKPiAr CXByaXYgPSBremFsbG9jKHNpemVvZigqcHJpdiksIEdGUF9LRVJORUwpOwo+ICsJaWYgKCFwcml2 KQo+ICsJCXJldHVybiAtRU5PTUVNOwo+ICsKPiArCXByaXYtPmRldiA9IGRldjsKPiArCWRybSA9 ICZwcml2LT5kcm07Cj4gKwlkcm0tPmRldl9wcml2YXRlID0gcHJpdjsKPiArCj4gKwlwbGF0Zm9y bV9zZXRfZHJ2ZGF0YShwZGV2LCBwcml2KTsKPiArCj4gKwlyZXQgPSBkZXZtX2RybV9kZXZfaW5p dChkZXYsIGRybSwgJmluZ2VuaWNfZHJtX2RyaXZlcl9kYXRhKTsKPiArCWlmIChyZXQpIHsKPiAr CQlrZnJlZShwcml2KTsKPiArCQlyZXR1cm4gcmV0Owo+ICsJfQo+ICsKPiArCWRybV9tb2RlX2Nv bmZpZ19pbml0KGRybSk7Cj4gKwlkcm0tPm1vZGVfY29uZmlnLm1pbl93aWR0aCA9IDA7Cj4gKwlk cm0tPm1vZGVfY29uZmlnLm1pbl9oZWlnaHQgPSAwOwo+ICsJZHJtLT5tb2RlX2NvbmZpZy5tYXhf d2lkdGggPSA4MDA7Cj4gKwlkcm0tPm1vZGVfY29uZmlnLm1heF9oZWlnaHQgPSA2MDA7Cj4gKwlk cm0tPm1vZGVfY29uZmlnLmZ1bmNzID0gJmluZ2VuaWNfZHJtX21vZGVfY29uZmlnX2Z1bmNzOwo+ ICsKPiArCW1lbSA9IHBsYXRmb3JtX2dldF9yZXNvdXJjZShwZGV2LCBJT1JFU09VUkNFX01FTSwg MCk7Cj4gKwliYXNlID0gZGV2bV9pb3JlbWFwX3Jlc291cmNlKGRldiwgbWVtKTsKPiArCWlmIChJ U19FUlIoYmFzZSkpIHsKPiArCQlkZXZfZXJyKGRldiwgIkZhaWxlZCB0byBnZXQgbWVtb3J5IHJl c291cmNlIik7Cj4gKwkJcmV0dXJuIFBUUl9FUlIoYmFzZSk7Cj4gKwl9Cj4gKwo+ICsJcHJpdi0+ bWFwID0gZGV2bV9yZWdtYXBfaW5pdF9tbWlvKGRldiwgYmFzZSwKPiArCQkJCQkgICZpbmdlbmlj X2RybV9yZWdtYXBfY29uZmlnKTsKPiArCWlmIChJU19FUlIocHJpdi0+bWFwKSkgewo+ICsJCWRl dl9lcnIoZGV2LCAiRmFpbGVkIHRvIGNyZWF0ZSByZWdtYXAiKTsKPiArCQlyZXR1cm4gUFRSX0VS Uihwcml2LT5tYXApOwo+ICsJfQo+ICsKPiArCWlycSA9IHBsYXRmb3JtX2dldF9pcnEocGRldiwg MCk7Cj4gKwlpZiAoaXJxIDwgMCkgewo+ICsJCWRldl9lcnIoZGV2LCAiRmFpbGVkIHRvIGdldCBw bGF0Zm9ybSBpcnEiKTsKPiArCQlyZXR1cm4gaXJxOwo+ICsJfQo+ICsKPiArCWlmIChzb2NfaW5m by0+bmVlZHNfZGV2X2Nsaykgewo+ICsJCXByaXYtPmxjZF9jbGsgPSBkZXZtX2Nsa19nZXQoZGV2 LCAibGNkIik7Cj4gKwkJaWYgKElTX0VSUihwcml2LT5sY2RfY2xrKSkgewo+ICsJCQlkZXZfZXJy KGRldiwgIkZhaWxlZCB0byBnZXQgbGNkIGNsb2NrIik7Cj4gKwkJCXJldHVybiBQVFJfRVJSKHBy aXYtPmxjZF9jbGspOwo+ICsJCX0KPiArCX0KPiArCj4gKwlwcml2LT5waXhfY2xrID0gZGV2bV9j bGtfZ2V0KGRldiwgImxjZF9wY2xrIik7Cj4gKwlpZiAoSVNfRVJSKHByaXYtPnBpeF9jbGspKSB7 Cj4gKwkJZGV2X2VycihkZXYsICJGYWlsZWQgdG8gZ2V0IHBpeGVsIGNsb2NrIik7Cj4gKwkJcmV0 dXJuIFBUUl9FUlIocHJpdi0+cGl4X2Nsayk7Cj4gKwl9Cj4gKwo+ICsJcmV0ID0gZHJtX29mX2Zp bmRfcGFuZWxfb3JfYnJpZGdlKGRldi0+b2Zfbm9kZSwgMCwgMCwgJnBhbmVsLCAmYnJpZGdlKTsK PiArCWlmIChyZXQpIHsKPiArCQlpZiAocmV0ICE9IC1FUFJPQkVfREVGRVIpCj4gKwkJCWRldl9l cnIoZGV2LCAiRmFpbGVkIHRvIGdldCBwYW5lbCBoYW5kbGUiKTsKPiArCQlyZXR1cm4gcmV0Owo+ ICsJfQo+ICsKPiArCWlmIChwYW5lbCkgewo+ICsJCWJyaWRnZSA9IGRldm1fZHJtX3BhbmVsX2Jy aWRnZV9hZGQoZGV2LCBwYW5lbCwKPiArCQkJCQkJICAgRFJNX01PREVfQ09OTkVDVE9SX1Vua25v d24pOwo+ICsJfQo+ICsKPiArCWlmIChicmlkZ2UpIHsKPiArCQlvZl9wcm9wZXJ0eV9yZWFkX3Uz MihicmlkZ2UtPm9mX25vZGUsICJpbmdlbmljLGxjZC1tb2RlIiwKPiArCQkJCSAgICAgJnByaXYt PmxjZF9tb2RlKTsKPiArCX0KPiArCj4gKwlwcml2LT5kbWFfaHdkZXNjID0gZG1hX2FsbG9jX2Nv aGVyZW50KGRldiwgc2l6ZW9mKCpwcml2LT5kbWFfaHdkZXNjKSwKPiArCQkJCQkgICAgICAmcHJp di0+ZG1hX2h3ZGVzY19waHlzLAo+ICsJCQkJCSAgICAgIEdGUF9LRVJORUwpOwo+ICsJaWYgKCFw cml2LT5kbWFfaHdkZXNjKQo+ICsJCXJldHVybiAtRU5PTUVNOwo+ICsKPiArCXJldCA9IGRldm1f YWRkX2FjdGlvbl9vcl9yZXNldChkZXYsIGluZ2VuaWNfZHJtX2ZyZWVfZG1hX2h3ZGVzYywgcHJp dik7Cj4gKwlpZiAocmV0KQo+ICsJCXJldHVybiByZXQ7Cj4gKwo+ICsJcHJpdi0+ZG1hX2h3ZGVz Yy0+bmV4dCA9IHByaXYtPmRtYV9od2Rlc2NfcGh5czsKPiArCXByaXYtPmRtYV9od2Rlc2MtPmlk ID0gMHhkZWFmYmVhZDsKPiArCj4gKwlkcm1fcGxhbmVfaGVscGVyX2FkZCgmcHJpdi0+cHJpbWFy eSwgJmluZ2VuaWNfZHJtX3BsYW5lX2hlbHBlcl9mdW5jcyk7Cj4gKwo+ICsJcmV0ID0gZHJtX3Vu aXZlcnNhbF9wbGFuZV9pbml0KGRybSwgJnByaXYtPnByaW1hcnksCj4gKwkJCQkgICAgICAgMCwg JmluZ2VuaWNfZHJtX3ByaW1hcnlfcGxhbmVfZnVuY3MsCj4gKwkJCQkgICAgICAgaW5nZW5pY19k cm1fcHJpbWFyeV9mb3JtYXRzLAo+ICsJCQkJICAgICAgIEFSUkFZX1NJWkUoaW5nZW5pY19kcm1f cHJpbWFyeV9mb3JtYXRzKSwKPiArCQkJCSAgICAgICBOVUxMLCBEUk1fUExBTkVfVFlQRV9QUklN QVJZLCBOVUxMKTsKPiArCWlmIChyZXQpIHsKPiArCQlkZXZfZXJyKGRldiwgIkZhaWxlZCB0byBy ZWdpc3RlciBwcmltYXJ5IHBsYW5lOiAlaSIsIHJldCk7Cj4gKwkJcmV0dXJuIHJldDsKPiArCX0K PiArCj4gKwlkcm1fY3J0Y19oZWxwZXJfYWRkKCZwcml2LT5jcnRjLCAmaW5nZW5pY19kcm1fY3J0 Y19oZWxwZXJfZnVuY3MpOwo+ICsKPiArCXJldCA9IGRybV9jcnRjX2luaXRfd2l0aF9wbGFuZXMo ZHJtLCAmcHJpdi0+Y3J0YywgJnByaXYtPnByaW1hcnksCj4gKwkJCQkJTlVMTCwgJmluZ2VuaWNf ZHJtX2NydGNfZnVuY3MsIE5VTEwpOwo+ICsJaWYgKHJldCkgewo+ICsJCWRldl9lcnIoZGV2LCAi RmFpbGVkIHRvIGluaXQgQ1JUQzogJWkiLCByZXQpOwo+ICsJCXJldHVybiByZXQ7Cj4gKwl9Cj4g Kwo+ICsJcHJpdi0+ZW5jb2Rlci5wb3NzaWJsZV9jcnRjcyA9IDE7Cj4gKwo+ICsJZHJtX2VuY29k ZXJfaGVscGVyX2FkZCgmcHJpdi0+ZW5jb2RlciwKPiArCQkJICAgICAgICZpbmdlbmljX2RybV9l bmNvZGVyX2hlbHBlcl9mdW5jcyk7Cj4gKwo+ICsJcmV0ID0gZHJtX2VuY29kZXJfaW5pdChkcm0s ICZwcml2LT5lbmNvZGVyLCAmaW5nZW5pY19kcm1fZW5jb2Rlcl9mdW5jcywKPiArCQkJICAgICAg IERSTV9NT0RFX0VOQ09ERVJfRFBJLCBOVUxMKTsKPiArCWlmIChyZXQpIHsKPiArCQlkZXZfZXJy KGRldiwgIkZhaWxlZCB0byBpbml0IGVuY29kZXI6ICVpIiwgcmV0KTsKPiArCQlyZXR1cm4gcmV0 Owo+ICsJfQo+ICsKPiArCXJldCA9IGRybV9icmlkZ2VfYXR0YWNoKCZwcml2LT5lbmNvZGVyLCBi cmlkZ2UsIE5VTEwpOwo+ICsJaWYgKHJldCkgewo+ICsJCWRldl9lcnIoZGV2LCAiVW5hYmxlIHRv IGF0dGFjaCBicmlkZ2UiKTsKPiArCQlyZXR1cm4gcmV0Owo+ICsJfQo+ICsKPiArCXJldCA9IGRy bV9pcnFfaW5zdGFsbChkcm0sIGlycSk7Cj4gKwlpZiAocmV0KSB7Cj4gKwkJZGV2X2VycihkZXYs ICJVbmFibGUgdG8gaW5zdGFsbCBJUlEgaGFuZGxlciIpOwo+ICsJCXJldHVybiByZXQ7Cj4gKwl9 Cj4gKwo+ICsJcmV0ID0gZHJtX3ZibGFua19pbml0KGRybSwgMSk7Cj4gKwlpZiAocmV0KSB7Cj4g KwkJZGV2X2VycihkZXYsICJGYWlsZWQgY2FsbGluZyBkcm1fdmJsYW5rX2luaXQoKSIpOwo+ICsJ CXJldHVybiByZXQ7Cj4gKwl9Cj4gKwo+ICsJZHJtX21vZGVfY29uZmlnX3Jlc2V0KGRybSk7Cj4g Kwo+ICsJcmV0ID0gY2xrX3ByZXBhcmVfZW5hYmxlKHByaXYtPnBpeF9jbGspOwo+ICsJaWYgKHJl dCkgewo+ICsJCWRldl9lcnIoZGV2LCAiVW5hYmxlIHRvIHN0YXJ0IHBpeGVsIGNsb2NrIik7Cj4g KwkJcmV0dXJuIHJldDsKPiArCX0KPiArCj4gKwlpZiAocHJpdi0+bGNkX2Nsaykgewo+ICsJCXBh cmVudF9jbGsgPSBjbGtfZ2V0X3BhcmVudChwcml2LT5sY2RfY2xrKTsKPiArCQlwYXJlbnRfcmF0 ZSA9IGNsa19nZXRfcmF0ZShwYXJlbnRfY2xrKTsKPiArCj4gKwkJLyogTENEIERldmljZSBjbG9j ayBtdXN0IGJlIDN4IHRoZSBwaXhlbCBjbG9jayBmb3IgU1ROIHBhbmVscywKPiArCQkgKiBvciAx LjV4IHRoZSBwaXhlbCBjbG9jayBmb3IgVEZUIHBhbmVscy4gVG8gYXZvaWQgaGF2aW5nIHRvCj4g KwkJICogY2hlY2sgZm9yIHRoZSBMQ0QgZGV2aWNlIGNsb2NrIGV2ZXJ5dGltZSB3ZSBkbyBhIG1v ZGUgY2hhbmdlLAo+ICsJCSAqIHdlIHNldCB0aGUgTENEIGRldmljZSBjbG9jayB0byB0aGUgaGln aGVzdCByYXRlIHBvc3NpYmxlLgo+ICsJCSAqLwo+ICsJCXJldCA9IGNsa19zZXRfcmF0ZShwcml2 LT5sY2RfY2xrLCBwYXJlbnRfcmF0ZSk7Cj4gKwkJaWYgKHJldCkgewo+ICsJCQlkZXZfZXJyKGRl diwgIlVuYWJsZSB0byBzZXQgTENEIGNsb2NrIHJhdGUiKTsKPiArCQkJZ290byBlcnJfcGl4Y2xr X2Rpc2FibGU7Cj4gKwkJfQo+ICsKPiArCQlyZXQgPSBjbGtfcHJlcGFyZV9lbmFibGUocHJpdi0+ bGNkX2Nsayk7Cj4gKwkJaWYgKHJldCkgewo+ICsJCQlkZXZfZXJyKGRldiwgIlVuYWJsZSB0byBz dGFydCBsY2QgY2xvY2siKTsKPiArCQkJZ290byBlcnJfcGl4Y2xrX2Rpc2FibGU7Cj4gKwkJfQo+ ICsJfQo+ICsKPiArCXJldCA9IGRybV9kZXZfcmVnaXN0ZXIoZHJtLCAwKTsKPiArCWlmIChyZXQp IHsKPiArCQlkZXZfZXJyKGRldiwgIkZhaWxlZCB0byByZWdpc3RlciBEUk0gZHJpdmVyIik7Cj4g KwkJZ290byBlcnJfZGV2Y2xrX2Rpc2FibGU7Cj4gKwl9Cj4gKwo+ICsJcmV0ID0gZHJtX2ZiZGV2 X2dlbmVyaWNfc2V0dXAoZHJtLCAxNik7Cj4gKwlpZiAocmV0KQo+ICsJCWRldl93YXJuKGRldiwg IlVuYWJsZSB0byBzdGFydCBmYmRldiBlbXVsYXRpb246ICVpIiwgcmV0KTsKPiArCj4gKwlyZXR1 cm4gMDsKPiArCj4gK2Vycl9kZXZjbGtfZGlzYWJsZToKPiArCWlmIChwcml2LT5sY2RfY2xrKQo+ ICsJCWNsa19kaXNhYmxlX3VucHJlcGFyZShwcml2LT5sY2RfY2xrKTsKPiArZXJyX3BpeGNsa19k aXNhYmxlOgo+ICsJY2xrX2Rpc2FibGVfdW5wcmVwYXJlKHByaXYtPnBpeF9jbGspOwo+ICsJcmV0 dXJuIHJldDsKPiArfQo+ICsKPiArc3RhdGljIGludCBpbmdlbmljX2RybV9yZW1vdmUoc3RydWN0 IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiArewo+ICsJc3RydWN0IGluZ2VuaWNfZHJtICpwcml2 ID0gcGxhdGZvcm1fZ2V0X2RydmRhdGEocGRldik7Cj4gKwo+ICsJaWYgKHByaXYtPmxjZF9jbGsp Cj4gKwkJY2xrX2Rpc2FibGVfdW5wcmVwYXJlKHByaXYtPmxjZF9jbGspOwo+ICsJY2xrX2Rpc2Fi bGVfdW5wcmVwYXJlKHByaXYtPnBpeF9jbGspOwo+ICsKPiArCWRybV9kZXZfdW5yZWdpc3Rlcigm cHJpdi0+ZHJtKTsKPiArCWRybV9hdG9taWNfaGVscGVyX3NodXRkb3duKCZwcml2LT5kcm0pOwo+ ICsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IGp6X3NvY19p bmZvIGp6NDc0MF9zb2NfaW5mbyA9IHsKPiArCS5uZWVkc19kZXZfY2xrID0gdHJ1ZSwKPiArfTsK PiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qganpfc29jX2luZm8gano0NzI1Yl9zb2NfaW5mbyA9 IHsKPiArCS5uZWVkc19kZXZfY2xrID0gZmFsc2UsCj4gK307Cj4gKwo+ICtzdGF0aWMgY29uc3Qg c3RydWN0IG9mX2RldmljZV9pZCBpbmdlbmljX2RybV9vZl9tYXRjaFtdID0gewo+ICsJeyAuY29t cGF0aWJsZSA9ICJpbmdlbmljLGp6NDc0MC1sY2QiLCAuZGF0YSA9ICZqejQ3NDBfc29jX2luZm8g fSwKPiArCXsgLmNvbXBhdGlibGUgPSAiaW5nZW5pYyxqejQ3MjViLWxjZCIsIC5kYXRhID0gJmp6 NDcyNWJfc29jX2luZm8gfSwKPiArCXsgLyogc2VudGluZWwgKi8gfSwKPiArfTsKPiArCj4gK3N0 YXRpYyBzdHJ1Y3QgcGxhdGZvcm1fZHJpdmVyIGluZ2VuaWNfZHJtX2RyaXZlciA9IHsKPiArCS5k cml2ZXIgPSB7Cj4gKwkJLm5hbWUgPSAiaW5nZW5pYy1kcm0iLAo+ICsJCS5vZl9tYXRjaF90YWJs ZSA9IG9mX21hdGNoX3B0cihpbmdlbmljX2RybV9vZl9tYXRjaCksCj4gKwl9LAo+ICsJLnByb2Jl ID0gaW5nZW5pY19kcm1fcHJvYmUsCj4gKwkucmVtb3ZlID0gaW5nZW5pY19kcm1fcmVtb3ZlLAo+ ICt9Owo+ICttb2R1bGVfcGxhdGZvcm1fZHJpdmVyKGluZ2VuaWNfZHJtX2RyaXZlcik7Cj4gKwo+ ICtNT0RVTEVfQVVUSE9SKCJQYXVsIENlcmN1ZWlsIDxwYXVsQGNyYXBvdWlsbG91Lm5ldD4iKTsK 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APjAAAVxPWbn3HDEhbjLwzlr1UtAnt5+Ir2jzZBik+l0aAjUCFiN27EB gAtjaapr0kjIDwl8LAL94zkfYA== X-Google-Smtp-Source: APXvYqxKS1F5m6cPJMa24n9u3SdqeIZiE32EdxOdL11AxWqEEnAiovKwPesk3Aycr2b5FnE12WW6Uw== X-Received: by 2002:a50:8822:: with SMTP id b31mr13103866edb.53.1555344469262; Mon, 15 Apr 2019 09:07:49 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:569e:0:3106:d637:d723:e855]) by smtp.gmail.com with ESMTPSA id c9sm8162713ejb.1.2019.04.15.09.07.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Apr 2019 09:07:48 -0700 (PDT) Date: Mon, 15 Apr 2019 18:07:46 +0200 From: Daniel Vetter To: Paul Cercueil Cc: David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , Maarten Lankhorst , Maxime Ripard , Sean Paul , od@zcrc.me, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 3/3] DRM: Add KMS driver for the Ingenic JZ47xx SoCs Message-ID: <20190415160746.GE2665@phenom.ffwll.local> Mail-Followup-To: Paul Cercueil , David Airlie , Rob Herring , Mark Rutland , Maarten Lankhorst , Maxime Ripard , Sean Paul , od@zcrc.me, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20190414200824.28348-1-paul@crapouillou.net> <20190414200824.28348-3-paul@crapouillou.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190414200824.28348-3-paul@crapouillou.net> X-Operating-System: Linux phenom 4.19.0-1-amd64 User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Apr 14, 2019 at 10:08:24PM +0200, Paul Cercueil wrote: > Add a KMS driver for the Ingenic JZ47xx family of SoCs. > This driver is meant to replace the aging jz4740-fb driver. > > Signed-off-by: Paul Cercueil > Tested-by: Artur Rojek Please put somewhere in your commit message why you're not using the simple pipe helpers - I had to recheck that from previous discussions :-) -Daniel > --- > > Notes: > v2: - Remove custom handling of panel. The panel is now discovered using > the standard API. > - Lots of small tweaks suggested by upstream > > v3: - Use devm_drm_dev_init() > - Update compatible strings to -lcd instead of -drm > - Add destroy() callbacks to plane and crtc > - The ingenic,lcd-mode is now read from the bridge's DT node > > drivers/gpu/drm/Kconfig | 2 + > drivers/gpu/drm/Makefile | 1 + > drivers/gpu/drm/ingenic/Kconfig | 16 + > drivers/gpu/drm/ingenic/Makefile | 1 + > drivers/gpu/drm/ingenic/ingenic-drm.c | 808 ++++++++++++++++++++++++++++++++++ > 5 files changed, 828 insertions(+) > create mode 100644 drivers/gpu/drm/ingenic/Kconfig > create mode 100644 drivers/gpu/drm/ingenic/Makefile > create mode 100644 drivers/gpu/drm/ingenic/ingenic-drm.c > > diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig > index 39d5f7562f1c..6863223c61d5 100644 > --- a/drivers/gpu/drm/Kconfig > +++ b/drivers/gpu/drm/Kconfig > @@ -307,6 +307,8 @@ source "drivers/gpu/drm/sti/Kconfig" > > source "drivers/gpu/drm/imx/Kconfig" > > +source "drivers/gpu/drm/ingenic/Kconfig" > + > source "drivers/gpu/drm/v3d/Kconfig" > > source "drivers/gpu/drm/vc4/Kconfig" > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile > index 3d0c75cd687c..1c2aca7965bd 100644 > --- a/drivers/gpu/drm/Makefile > +++ b/drivers/gpu/drm/Makefile > @@ -95,6 +95,7 @@ obj-$(CONFIG_DRM_TEGRA) += tegra/ > obj-$(CONFIG_DRM_STM) += stm/ > obj-$(CONFIG_DRM_STI) += sti/ > obj-$(CONFIG_DRM_IMX) += imx/ > +obj-$(CONFIG_DRM_INGENIC) += ingenic/ > obj-$(CONFIG_DRM_MEDIATEK) += mediatek/ > obj-$(CONFIG_DRM_MESON) += meson/ > obj-y += i2c/ > diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig > new file mode 100644 > index 000000000000..d82c3d37ec9c > --- /dev/null > +++ b/drivers/gpu/drm/ingenic/Kconfig > @@ -0,0 +1,16 @@ > +config DRM_INGENIC > + tristate "DRM Support for Ingenic SoCs" > + depends on MIPS || COMPILE_TEST > + depends on DRM > + depends on CMA > + depends on OF > + select DRM_BRIDGE > + select DRM_PANEL_BRIDGE > + select DRM_KMS_HELPER > + select DRM_KMS_CMA_HELPER > + select DRM_GEM_CMA_HELPER > + select VT_HW_CONSOLE_BINDING if FRAMEBUFFER_CONSOLE > + help > + Choose this option for DRM support for the Ingenic SoCs. > + > + If M is selected the module will be called ingenic-drm. > diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile > new file mode 100644 > index 000000000000..11cac42ce0bb > --- /dev/null > +++ b/drivers/gpu/drm/ingenic/Makefile > @@ -0,0 +1 @@ > +obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c b/drivers/gpu/drm/ingenic/ingenic-drm.c > new file mode 100644 > index 000000000000..6b52ef2f9790 > --- /dev/null > +++ b/drivers/gpu/drm/ingenic/ingenic-drm.c > @@ -0,0 +1,808 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Ingenic JZ47xx KMS driver > +// > +// Copyright (C) 2019, Paul Cercueil > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#define JZ_REG_LCD_CFG 0x00 > +#define JZ_REG_LCD_VSYNC 0x04 > +#define JZ_REG_LCD_HSYNC 0x08 > +#define JZ_REG_LCD_VAT 0x0C > +#define JZ_REG_LCD_DAH 0x10 > +#define JZ_REG_LCD_DAV 0x14 > +#define JZ_REG_LCD_PS 0x18 > +#define JZ_REG_LCD_CLS 0x1C > +#define JZ_REG_LCD_SPL 0x20 > +#define JZ_REG_LCD_REV 0x24 > +#define JZ_REG_LCD_CTRL 0x30 > +#define JZ_REG_LCD_STATE 0x34 > +#define JZ_REG_LCD_IID 0x38 > +#define JZ_REG_LCD_DA0 0x40 > +#define JZ_REG_LCD_SA0 0x44 > +#define JZ_REG_LCD_FID0 0x48 > +#define JZ_REG_LCD_CMD0 0x4C > +#define JZ_REG_LCD_DA1 0x50 > +#define JZ_REG_LCD_SA1 0x54 > +#define JZ_REG_LCD_FID1 0x58 > +#define JZ_REG_LCD_CMD1 0x5C > + > +#define JZ_LCD_CFG_SLCD BIT(31) > +#define JZ_LCD_CFG_PS_DISABLE BIT(23) > +#define JZ_LCD_CFG_CLS_DISABLE BIT(22) > +#define JZ_LCD_CFG_SPL_DISABLE BIT(21) > +#define JZ_LCD_CFG_REV_DISABLE BIT(20) > +#define JZ_LCD_CFG_HSYNCM BIT(19) > +#define JZ_LCD_CFG_PCLKM BIT(18) > +#define JZ_LCD_CFG_INV BIT(17) > +#define JZ_LCD_CFG_SYNC_DIR BIT(16) > +#define JZ_LCD_CFG_PS_POLARITY BIT(15) > +#define JZ_LCD_CFG_CLS_POLARITY BIT(14) > +#define JZ_LCD_CFG_SPL_POLARITY BIT(13) > +#define JZ_LCD_CFG_REV_POLARITY BIT(12) > +#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) > +#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) > +#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) > +#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) > +#define JZ_LCD_CFG_18_BIT BIT(7) > +#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) > +#define JZ_LCD_CFG_MODE_MASK 0xf > + > +#define JZ_LCD_VSYNC_VPS_OFFSET 16 > +#define JZ_LCD_VSYNC_VPE_OFFSET 0 > + > +#define JZ_LCD_HSYNC_HPS_OFFSET 16 > +#define JZ_LCD_HSYNC_HPE_OFFSET 0 > + > +#define JZ_LCD_VAT_HT_OFFSET 16 > +#define JZ_LCD_VAT_VT_OFFSET 0 > + > +#define JZ_LCD_DAH_HDS_OFFSET 16 > +#define JZ_LCD_DAH_HDE_OFFSET 0 > + > +#define JZ_LCD_DAV_VDS_OFFSET 16 > +#define JZ_LCD_DAV_VDE_OFFSET 0 > + > +#define JZ_LCD_CTRL_BURST_4 (0x0 << 28) > +#define JZ_LCD_CTRL_BURST_8 (0x1 << 28) > +#define JZ_LCD_CTRL_BURST_16 (0x2 << 28) > +#define JZ_LCD_CTRL_RGB555 BIT(27) > +#define JZ_LCD_CTRL_OFUP BIT(26) > +#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24) > +#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24) > +#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24) > +#define JZ_LCD_CTRL_PDD_MASK (0xff << 16) > +#define JZ_LCD_CTRL_EOF_IRQ BIT(13) > +#define JZ_LCD_CTRL_SOF_IRQ BIT(12) > +#define JZ_LCD_CTRL_OFU_IRQ BIT(11) > +#define JZ_LCD_CTRL_IFU0_IRQ BIT(10) > +#define JZ_LCD_CTRL_IFU1_IRQ BIT(9) > +#define JZ_LCD_CTRL_DD_IRQ BIT(8) > +#define JZ_LCD_CTRL_QDD_IRQ BIT(7) > +#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6) > +#define JZ_LCD_CTRL_LSB_FISRT BIT(5) > +#define JZ_LCD_CTRL_DISABLE BIT(4) > +#define JZ_LCD_CTRL_ENABLE BIT(3) > +#define JZ_LCD_CTRL_BPP_1 0x0 > +#define JZ_LCD_CTRL_BPP_2 0x1 > +#define JZ_LCD_CTRL_BPP_4 0x2 > +#define JZ_LCD_CTRL_BPP_8 0x3 > +#define JZ_LCD_CTRL_BPP_15_16 0x4 > +#define JZ_LCD_CTRL_BPP_18_24 0x5 > +#define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | (0x7 << 0)) > + > +#define JZ_LCD_CMD_SOF_IRQ BIT(31) > +#define JZ_LCD_CMD_EOF_IRQ BIT(30) > +#define JZ_LCD_CMD_ENABLE_PAL BIT(28) > + > +#define JZ_LCD_SYNC_MASK 0x3ff > + > +#define JZ_LCD_STATE_EOF_IRQ BIT(5) > +#define JZ_LCD_STATE_SOF_IRQ BIT(4) > +#define JZ_LCD_STATE_DISABLED BIT(0) > + > +struct ingenic_dma_hwdesc { > + u32 next; > + u32 addr; > + u32 id; > + u32 cmd; > +} __packed; > + > +struct jz_soc_info { > + bool needs_dev_clk; > +}; > + > +struct ingenic_drm { > + struct drm_device drm; > + struct drm_plane primary; > + struct drm_crtc crtc; > + struct drm_encoder encoder; > + > + struct device *dev; > + struct regmap *map; > + struct clk *lcd_clk, *pix_clk; > + > + u32 lcd_mode; > + > + struct ingenic_dma_hwdesc *dma_hwdesc; > + dma_addr_t dma_hwdesc_phys; > +}; > + > +static const u32 ingenic_drm_primary_formats[] = { > + DRM_FORMAT_XRGB1555, > + DRM_FORMAT_RGB565, > + DRM_FORMAT_XRGB8888, > +}; > + > +static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) > +{ > + switch (reg) { > + case JZ_REG_LCD_IID: > + case JZ_REG_LCD_SA0: > + case JZ_REG_LCD_FID0: > + case JZ_REG_LCD_CMD0: > + case JZ_REG_LCD_SA1: > + case JZ_REG_LCD_FID1: > + case JZ_REG_LCD_CMD1: > + return false; > + default: > + return true; > + } > +} > + > +static const struct regmap_config ingenic_drm_regmap_config = { > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > + > + .max_register = JZ_REG_LCD_CMD1, > + .writeable_reg = ingenic_drm_writeable_reg, > +}; > + > +static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm) > +{ > + return container_of(drm, struct ingenic_drm, drm); > +} > + > +static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc) > +{ > + return container_of(crtc, struct ingenic_drm, crtc); > +} > + > +static inline struct ingenic_drm * > +drm_encoder_get_priv(struct drm_encoder *encoder) > +{ > + return container_of(encoder, struct ingenic_drm, encoder); > +} > + > +static inline struct ingenic_drm *drm_plane_get_priv(struct drm_plane *plane) > +{ > + return container_of(plane, struct ingenic_drm, primary); > +} > + > +static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, > + struct drm_crtc_state *state) > +{ > + struct ingenic_drm *priv = drm_crtc_get_priv(crtc); > + > + regmap_write(priv->map, JZ_REG_LCD_STATE, 0); > + > + regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, > + JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, > + JZ_LCD_CTRL_ENABLE); > + > + drm_crtc_vblank_on(crtc); > +} > + > +static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc, > + struct drm_crtc_state *state) > +{ > + struct ingenic_drm *priv = drm_crtc_get_priv(crtc); > + unsigned int var; > + > + drm_crtc_vblank_off(crtc); > + > + regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, > + JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE); > + > + regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var, > + var & JZ_LCD_STATE_DISABLED, > + 1000, 0); > +} > + > +static inline bool ingenic_drm_lcd_is_special_mode(u32 mode) > +{ > + switch (mode) { > + case JZ_LCD_SPECIAL_TFT_1: > + case JZ_LCD_SPECIAL_TFT_2: > + case JZ_LCD_SPECIAL_TFT_3: > + return true; > + default: > + return false; > + } > +} > + > +static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, > + struct drm_display_mode *mode) > +{ > + unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht; > + > + vpe = mode->vsync_end - mode->vsync_start; > + vds = mode->vtotal - mode->vsync_start; > + vde = vds + mode->vdisplay; > + vt = vde + mode->vsync_start - mode->vdisplay; > + > + hpe = mode->hsync_end - mode->hsync_start; > + hds = mode->htotal - mode->hsync_start; > + hde = hds + mode->hdisplay; > + ht = hde + mode->hsync_start - mode->hdisplay; > + > + regmap_write(priv->map, JZ_REG_LCD_VSYNC, > + 0 << JZ_LCD_VSYNC_VPS_OFFSET | > + vpe << JZ_LCD_VSYNC_VPE_OFFSET); > + > + regmap_write(priv->map, JZ_REG_LCD_HSYNC, > + 0 << JZ_LCD_HSYNC_HPS_OFFSET | > + hpe << JZ_LCD_HSYNC_HPE_OFFSET); > + > + regmap_write(priv->map, JZ_REG_LCD_VAT, > + ht << JZ_LCD_VAT_HT_OFFSET | > + vt << JZ_LCD_VAT_VT_OFFSET); > + > + regmap_write(priv->map, JZ_REG_LCD_DAH, > + hds << JZ_LCD_DAH_HDS_OFFSET | > + hde << JZ_LCD_DAH_HDE_OFFSET); > + regmap_write(priv->map, JZ_REG_LCD_DAV, > + vds << JZ_LCD_DAV_VDS_OFFSET | > + vde << JZ_LCD_DAV_VDE_OFFSET); > + > + if (ingenic_drm_lcd_is_special_mode(priv->lcd_mode)) { > + regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1)); > + regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1)); > + regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1)); > + regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16); > + } > +} > + > +static void ingenic_drm_crtc_update_ctrl(struct ingenic_drm *priv, > + unsigned int bpp) > +{ > + unsigned int ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16; > + > + switch (bpp) { > + case 1: > + ctrl |= JZ_LCD_CTRL_BPP_1; > + break; > + case 2: > + ctrl |= JZ_LCD_CTRL_BPP_2; > + break; > + case 4: > + ctrl |= JZ_LCD_CTRL_BPP_4; > + break; > + case 8: > + ctrl |= JZ_LCD_CTRL_BPP_8; > + break; > + case 15: > + ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */ > + case 16: > + ctrl |= JZ_LCD_CTRL_BPP_15_16; > + break; > + case 18: > + case 24: > + case 32: > + ctrl |= JZ_LCD_CTRL_BPP_18_24; > + break; > + default: > + break; > + } > + > + regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, > + JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16 | > + JZ_LCD_CTRL_BPP_MASK, ctrl); > +} > + > +static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc, > + struct drm_crtc_state *state) > +{ > + struct ingenic_drm *priv = drm_crtc_get_priv(crtc); > + long rate; > + > + if (!drm_atomic_crtc_needs_modeset(state)) > + return 0; > + > + rate = clk_round_rate(priv->pix_clk, > + state->adjusted_mode.clock * 1000); > + if (rate < 0) > + return rate; > + > + return 0; > +} > + > +static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, > + struct drm_crtc_state *oldstate) > +{ > + struct ingenic_drm *priv = drm_crtc_get_priv(crtc); > + struct drm_crtc_state *state = crtc->state; > + struct drm_pending_vblank_event *event = state->event; > + struct drm_framebuffer *drm_fb = crtc->primary->state->fb; > + const struct drm_format_info *finfo; > + > + if (drm_atomic_crtc_needs_modeset(state)) { > + finfo = drm_format_info(drm_fb->format->format); > + > + ingenic_drm_crtc_update_timings(priv, &state->mode); > + ingenic_drm_crtc_update_ctrl(priv, finfo->depth); > + > + clk_set_rate(priv->pix_clk, state->adjusted_mode.clock * 1000); > + > + regmap_write(priv->map, JZ_REG_LCD_DA0, priv->dma_hwdesc->next); > + } > + > + if (event) { > + state->event = NULL; > + > + spin_lock_irq(&crtc->dev->event_lock); > + if (drm_crtc_vblank_get(crtc) == 0) > + drm_crtc_arm_vblank_event(crtc, event); > + else > + drm_crtc_send_vblank_event(crtc, event); > + spin_unlock_irq(&crtc->dev->event_lock); > + } > +} > + > +static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, > + struct drm_plane_state *oldstate) > +{ > + struct ingenic_drm *priv = drm_plane_get_priv(plane); > + struct drm_plane_state *state = plane->state; > + const struct drm_format_info *finfo; > + unsigned int width, height; > + > + finfo = drm_format_info(state->fb->format->format); > + width = state->crtc->state->adjusted_mode.hdisplay; > + height = state->crtc->state->adjusted_mode.vdisplay; > + > + priv->dma_hwdesc->addr = drm_fb_cma_get_gem_addr(state->fb, state, 0); > + > + priv->dma_hwdesc->cmd = width * height * ((finfo->depth + 7) / 8) / 4; > + priv->dma_hwdesc->cmd |= JZ_LCD_CMD_EOF_IRQ; > +} > + > +static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, > + struct drm_crtc_state *crtc_state, > + struct drm_connector_state *conn_state) > +{ > + struct ingenic_drm *priv = drm_encoder_get_priv(encoder); > + struct drm_display_mode *mode = &crtc_state->adjusted_mode; > + u32 bus_flags = conn_state->connector->display_info.bus_flags; > + unsigned int cfg = priv->lcd_mode; > + > + if (mode->flags & DRM_MODE_FLAG_NHSYNC) > + cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; > + if (mode->flags & DRM_MODE_FLAG_NVSYNC) > + cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; > + if (bus_flags & DRM_BUS_FLAG_DE_LOW) > + cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; > + if (bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE) > + cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; > + > + if (ingenic_drm_lcd_is_special_mode(priv->lcd_mode)) { > + /* TODO: Is that valid for all special modes? */ > + cfg |= JZ_LCD_CFG_REV_POLARITY; > + } else { > + cfg |= JZ_LCD_CFG_PS_DISABLE > + | JZ_LCD_CFG_CLS_DISABLE > + | JZ_LCD_CFG_SPL_DISABLE > + | JZ_LCD_CFG_REV_DISABLE; > + } > + > + regmap_write(priv->map, JZ_REG_LCD_CFG, cfg); > +} > + > +static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg) > +{ > + struct ingenic_drm *priv = arg; > + unsigned int state; > + > + regmap_read(priv->map, JZ_REG_LCD_STATE, &state); > + > + regmap_update_bits(priv->map, JZ_REG_LCD_STATE, > + JZ_LCD_STATE_EOF_IRQ, 0); > + > + if (state & JZ_LCD_STATE_EOF_IRQ) > + drm_crtc_handle_vblank(&priv->crtc); > + > + return IRQ_HANDLED; > +} > + > +static void ingenic_drm_release(struct drm_device *drm) > +{ > + struct ingenic_drm *priv = drm_device_get_priv(drm); > + > + drm_mode_config_cleanup(drm); > + drm_dev_fini(drm); > + kfree(priv); > +} > + > +static int ingenic_drm_enable_vblank(struct drm_crtc *crtc) > +{ > + struct ingenic_drm *priv = drm_crtc_get_priv(crtc); > + > + regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, > + JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ); > + > + return 0; > +} > + > +static void ingenic_drm_disable_vblank(struct drm_crtc *crtc) > +{ > + struct ingenic_drm *priv = drm_crtc_get_priv(crtc); > + > + regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0); > +} > + > +DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops); > + > +static struct drm_driver ingenic_drm_driver_data = { > + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME > + | DRIVER_ATOMIC, > + .name = "ingenic-drm", > + .desc = "DRM module for Ingenic SoCs", > + .date = "20190228", > + .major = 1, > + .minor = 0, > + .patchlevel = 0, > + > + .fops = &ingenic_drm_fops, > + > + .dumb_create = drm_gem_cma_dumb_create, > + .gem_free_object_unlocked = drm_gem_cma_free_object, > + .gem_vm_ops = &drm_gem_cma_vm_ops, > + > + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, > + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, > + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, > + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, > + .gem_prime_vmap = drm_gem_cma_prime_vmap, > + .gem_prime_vunmap = drm_gem_cma_prime_vunmap, > + .gem_prime_mmap = drm_gem_cma_prime_mmap, > + > + .irq_handler = ingenic_drm_irq_handler, > + .release = ingenic_drm_release, > +}; > + > +static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = { > + .update_plane = drm_atomic_helper_update_plane, > + .disable_plane = drm_atomic_helper_disable_plane, > + .reset = drm_atomic_helper_plane_reset, > + .destroy = drm_plane_cleanup, > + > + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, > + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, > +}; > + > +static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = { > + .set_config = drm_atomic_helper_set_config, > + .page_flip = drm_atomic_helper_page_flip, > + .reset = drm_atomic_helper_crtc_reset, > + .destroy = drm_crtc_cleanup, > + > + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, > + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, > + > + .enable_vblank = ingenic_drm_enable_vblank, > + .disable_vblank = ingenic_drm_disable_vblank, > + > + .gamma_set = drm_atomic_helper_legacy_gamma_set, > +}; > + > +static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = { > + .atomic_update = ingenic_drm_plane_atomic_update, > + .prepare_fb = drm_gem_fb_prepare_fb, > +}; > + > +static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = { > + .atomic_enable = ingenic_drm_crtc_atomic_enable, > + .atomic_disable = ingenic_drm_crtc_atomic_disable, > + .atomic_flush = ingenic_drm_crtc_atomic_flush, > + .atomic_check = ingenic_drm_crtc_atomic_check, > +}; > + > +static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = { > + .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set, > +}; > + > +static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = { > + .fb_create = drm_gem_fb_create, > + .output_poll_changed = drm_fb_helper_output_poll_changed, > + .atomic_check = drm_atomic_helper_check, > + .atomic_commit = drm_atomic_helper_commit, > +}; > + > +static const struct drm_encoder_funcs ingenic_drm_encoder_funcs = { > + .destroy = drm_encoder_cleanup, > +}; > + > +static void ingenic_drm_free_dma_hwdesc(void *d) > +{ > + struct ingenic_drm *priv = d; > + > + dma_free_coherent(priv->dev, sizeof(*priv->dma_hwdesc), > + priv->dma_hwdesc, priv->dma_hwdesc_phys); > +} > + > +static int ingenic_drm_probe(struct platform_device *pdev) > +{ > + const struct jz_soc_info *soc_info; > + struct device *dev = &pdev->dev; > + struct ingenic_drm *priv; > + struct clk *parent_clk; > + struct drm_bridge *bridge; > + struct drm_panel *panel; > + struct drm_device *drm; > + struct resource *mem; > + void __iomem *base; > + long parent_rate; > + int ret, irq; > + > + soc_info = of_device_get_match_data(dev); > + if (!soc_info) { > + dev_err(dev, "Missing platform data\n"); > + return -EINVAL; > + } > + > + priv = kzalloc(sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->dev = dev; > + drm = &priv->drm; > + drm->dev_private = priv; > + > + platform_set_drvdata(pdev, priv); > + > + ret = devm_drm_dev_init(dev, drm, &ingenic_drm_driver_data); > + if (ret) { > + kfree(priv); > + return ret; > + } > + > + drm_mode_config_init(drm); > + drm->mode_config.min_width = 0; > + drm->mode_config.min_height = 0; > + drm->mode_config.max_width = 800; > + drm->mode_config.max_height = 600; > + drm->mode_config.funcs = &ingenic_drm_mode_config_funcs; > + > + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + base = devm_ioremap_resource(dev, mem); > + if (IS_ERR(base)) { > + dev_err(dev, "Failed to get memory resource"); > + return PTR_ERR(base); > + } > + > + priv->map = devm_regmap_init_mmio(dev, base, > + &ingenic_drm_regmap_config); > + if (IS_ERR(priv->map)) { > + dev_err(dev, "Failed to create regmap"); > + return PTR_ERR(priv->map); > + } > + > + irq = platform_get_irq(pdev, 0); > + if (irq < 0) { > + dev_err(dev, "Failed to get platform irq"); > + return irq; > + } > + > + if (soc_info->needs_dev_clk) { > + priv->lcd_clk = devm_clk_get(dev, "lcd"); > + if (IS_ERR(priv->lcd_clk)) { > + dev_err(dev, "Failed to get lcd clock"); > + return PTR_ERR(priv->lcd_clk); > + } > + } > + > + priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); > + if (IS_ERR(priv->pix_clk)) { > + dev_err(dev, "Failed to get pixel clock"); > + return PTR_ERR(priv->pix_clk); > + } > + > + ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, &panel, &bridge); > + if (ret) { > + if (ret != -EPROBE_DEFER) > + dev_err(dev, "Failed to get panel handle"); > + return ret; > + } > + > + if (panel) { > + bridge = devm_drm_panel_bridge_add(dev, panel, > + DRM_MODE_CONNECTOR_Unknown); > + } > + > + if (bridge) { > + of_property_read_u32(bridge->of_node, "ingenic,lcd-mode", > + &priv->lcd_mode); > + } > + > + priv->dma_hwdesc = dma_alloc_coherent(dev, sizeof(*priv->dma_hwdesc), > + &priv->dma_hwdesc_phys, > + GFP_KERNEL); > + if (!priv->dma_hwdesc) > + return -ENOMEM; > + > + ret = devm_add_action_or_reset(dev, ingenic_drm_free_dma_hwdesc, priv); > + if (ret) > + return ret; > + > + priv->dma_hwdesc->next = priv->dma_hwdesc_phys; > + priv->dma_hwdesc->id = 0xdeafbead; > + > + drm_plane_helper_add(&priv->primary, &ingenic_drm_plane_helper_funcs); > + > + ret = drm_universal_plane_init(drm, &priv->primary, > + 0, &ingenic_drm_primary_plane_funcs, > + ingenic_drm_primary_formats, > + ARRAY_SIZE(ingenic_drm_primary_formats), > + NULL, DRM_PLANE_TYPE_PRIMARY, NULL); > + if (ret) { > + dev_err(dev, "Failed to register primary plane: %i", ret); > + return ret; > + } > + > + drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs); > + > + ret = drm_crtc_init_with_planes(drm, &priv->crtc, &priv->primary, > + NULL, &ingenic_drm_crtc_funcs, NULL); > + if (ret) { > + dev_err(dev, "Failed to init CRTC: %i", ret); > + return ret; > + } > + > + priv->encoder.possible_crtcs = 1; > + > + drm_encoder_helper_add(&priv->encoder, > + &ingenic_drm_encoder_helper_funcs); > + > + ret = drm_encoder_init(drm, &priv->encoder, &ingenic_drm_encoder_funcs, > + DRM_MODE_ENCODER_DPI, NULL); > + if (ret) { > + dev_err(dev, "Failed to init encoder: %i", ret); > + return ret; > + } > + > + ret = drm_bridge_attach(&priv->encoder, bridge, NULL); > + if (ret) { > + dev_err(dev, "Unable to attach bridge"); > + return ret; > + } > + > + ret = drm_irq_install(drm, irq); > + if (ret) { > + dev_err(dev, "Unable to install IRQ handler"); > + return ret; > + } > + > + ret = drm_vblank_init(drm, 1); > + if (ret) { > + dev_err(dev, "Failed calling drm_vblank_init()"); > + return ret; > + } > + > + drm_mode_config_reset(drm); > + > + ret = clk_prepare_enable(priv->pix_clk); > + if (ret) { > + dev_err(dev, "Unable to start pixel clock"); > + return ret; > + } > + > + if (priv->lcd_clk) { > + parent_clk = clk_get_parent(priv->lcd_clk); > + parent_rate = clk_get_rate(parent_clk); > + > + /* LCD Device clock must be 3x the pixel clock for STN panels, > + * or 1.5x the pixel clock for TFT panels. To avoid having to > + * check for the LCD device clock everytime we do a mode change, > + * we set the LCD device clock to the highest rate possible. > + */ > + ret = clk_set_rate(priv->lcd_clk, parent_rate); > + if (ret) { > + dev_err(dev, "Unable to set LCD clock rate"); > + goto err_pixclk_disable; > + } > + > + ret = clk_prepare_enable(priv->lcd_clk); > + if (ret) { > + dev_err(dev, "Unable to start lcd clock"); > + goto err_pixclk_disable; > + } > + } > + > + ret = drm_dev_register(drm, 0); > + if (ret) { > + dev_err(dev, "Failed to register DRM driver"); > + goto err_devclk_disable; > + } > + > + ret = drm_fbdev_generic_setup(drm, 16); > + if (ret) > + dev_warn(dev, "Unable to start fbdev emulation: %i", ret); > + > + return 0; > + > +err_devclk_disable: > + if (priv->lcd_clk) > + clk_disable_unprepare(priv->lcd_clk); > +err_pixclk_disable: > + clk_disable_unprepare(priv->pix_clk); > + return ret; > +} > + > +static int ingenic_drm_remove(struct platform_device *pdev) > +{ > + struct ingenic_drm *priv = platform_get_drvdata(pdev); > + > + if (priv->lcd_clk) > + clk_disable_unprepare(priv->lcd_clk); > + clk_disable_unprepare(priv->pix_clk); > + > + drm_dev_unregister(&priv->drm); > + drm_atomic_helper_shutdown(&priv->drm); > + > + return 0; > +} > + > +static const struct jz_soc_info jz4740_soc_info = { > + .needs_dev_clk = true, > +}; > + > +static const struct jz_soc_info jz4725b_soc_info = { > + .needs_dev_clk = false, > +}; > + > +static const struct of_device_id ingenic_drm_of_match[] = { > + { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, > + { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, > + { /* sentinel */ }, > +}; > + > +static struct platform_driver ingenic_drm_driver = { > + .driver = { > + .name = "ingenic-drm", > + .of_match_table = of_match_ptr(ingenic_drm_of_match), > + }, > + .probe = ingenic_drm_probe, > + .remove = ingenic_drm_remove, > +}; > +module_platform_driver(ingenic_drm_driver); > + > +MODULE_AUTHOR("Paul Cercueil "); > +MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n"); > +MODULE_LICENSE("GPL v2"); > -- > 2.11.0 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch