Re: [PATCH V2 18/28] PCI: tegra: Program AFI_CACHE* registers only for Tegra20

[Thierry Reding <thierry.reding@gmail.com>]

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On Tue, Apr 23, 2019 at 02:58:15PM +0530, Manikanta Maddireddy wrote:
> Cacheable upstream transactions are supported in Tegra20 and Tegra186 only.
> AFI_CACHE* registers are available in Tegra20 to support cacheable upstream
> transactions. In Tegra186, AFI_AXCACHE register is defined instead of
> AFI_CACHE* to be in line with its MSS design. Therefore, program AFI_CACHE*
> registers only for Tegra20.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> V2: Used soc variable for comparision instead of compatible string.
> 
>  drivers/pci/controller/pci-tegra.c | 13 ++++++++-----
>  1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> index f74930654443..9b841b0392ac 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -323,6 +323,7 @@ struct tegra_pcie_soc {
>  	bool program_deskew_time;
>  	bool raw_violation_fixup;
>  	bool update_fc_timer;
> +	bool has_cache_bars;
>  	struct {
>  		struct {
>  			u32 rp_ectl_2_r1;
> @@ -932,11 +933,13 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
>  	afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
>  	afi_writel(pcie, 0, AFI_FPCI_BAR5);
>  
> -	/* map all upstream transactions as uncached */
> -	afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
> -	afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
> -	afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
> -	afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
> +	if (pcie->soc->has_cache_bars) {
> +		/* map all upstream transactions as uncached */
> +		afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
> +		afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
> +		afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
> +		afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
> +	}
>  
>  	/* MSI translations are setup only when needed */
>  	afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);

You need to squash the below into this patch. If I do that, then
TrimSlice works again.

Thierry

--- >8 ---
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 7071fd026a80..fc61074f6886 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -2530,6 +2530,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
  .program_deskew_time = false,
  .raw_violation_fixup = false,
  .update_fc_timer = false,
+ .has_cache_bars = true,
  .ectl.enable = false,
 };

@@ -2558,6 +2559,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
  .program_deskew_time = false,
  .raw_violation_fixup = false,
  .update_fc_timer = false,
+ .has_cache_bars = false,
  .ectl.enable = false,
 };

@@ -2581,6 +2583,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
  .program_deskew_time = false,
  .raw_violation_fixup = true,
  .update_fc_timer = false,
+ .has_cache_bars = false,
  .ectl.enable = false,
 };

@@ -2604,6 +2607,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
  .program_deskew_time = true,
  .raw_violation_fixup = false,
  .update_fc_timer = true,
+ .has_cache_bars = false,
  .ectl = {
   .regs = {
    .rp_ectl_2_r1 = 0x0000000f,
@@ -2645,6 +2649,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
  .program_deskew_time = false,
  .raw_violation_fixup = false,
  .update_fc_timer = false,
+ .has_cache_bars = false,
  .ectl.enable = false,
 };


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