diff for duplicates of <20190428114515.32683-2-npiggin@gmail.com> diff --git a/a/1.txt b/N1/1.txt index a7be678..bdd30f7 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -712,7 +712,7 @@ index 4a860d3b9229..0fb2eb731a29 100644 - */ -power_enter_stop: -/* -- * Check if we are executing the lite variant with ESLì=0 +- * Check if we are executing the lite variant with ESL=EC=0 - */ - andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED - clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */ @@ -755,7 +755,7 @@ index 4a860d3b9229..0fb2eb731a29 100644 - * reason, so there is no point setting r12 to SRR1. - * - * Further, we clear r12 here, so that we don't accidentally enter the -- * HMI in pnv_wakeup_noloss() if the value of r12[42:45] = WAKE_HMI. +- * HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI. - */ - li r12, 0 - b pnv_wakeup_noloss @@ -1163,8 +1163,8 @@ index 4a860d3b9229..0fb2eb731a29 100644 - * { - * bool first_in_core, first_in_subcore; - * -- * first_in_core = (core_idle_state & IDLE_THREAD_BITS) = 0; -- * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) = 0; +- * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0; +- * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0; - * - * core_idle_state |= thread_in_core; - * } @@ -1179,12 +1179,12 @@ index 4a860d3b9229..0fb2eb731a29 100644 - * { - * bool first_in_core, first_in_subcore, winkle_state_lost; - * -- * first_in_core = (core_idle_state & IDLE_THREAD_BITS) = 0; -- * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) = 0; +- * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0; +- * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0; - * - * core_idle_state |= thread_in_core; - * -- * if ((core_idle_state & WINKLE_MASK) = (8 << WINKLE_COUNT_SIHFT)) +- * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT)) - * core_idle_state |= THREAD_WINKLE_BITS; - * core_idle_state -= 1 << WINKLE_COUNT_SHIFT; - * @@ -1629,8 +1629,10 @@ index e52f9b06dd9c..182112fd845a 100644 - * if available. - */ - if (default_stop_found) { -- pnv_deepest_stop_psscr_val - pnv_default_stop_val; -- pnv_deepest_stop_psscr_mask - pnv_default_stop_mask; +- pnv_deepest_stop_psscr_val = +- pnv_default_stop_val; +- pnv_deepest_stop_psscr_mask = +- pnv_default_stop_mask; - pr_warn("cpuidle-powernv: Offlined CPUs will stop with psscr = 0x%016llx\n", - pnv_deepest_stop_psscr_val); - } else { /* Fallback to snooze loop for CPU-Hotplug */ @@ -1810,7 +1812,7 @@ index e52f9b06dd9c..182112fd845a 100644 + *state &= ~thread; + + if (power7_fastsleep_workaround_entry) { -+ if ((*state & core_thread_mask) = 0) { ++ if ((*state & core_thread_mask) == 0) { + rc = opal_config_cpu_idle_state( + OPAL_CONFIG_IDLE_FASTSLEEP, + OPAL_CONFIG_IDLE_APPLY); @@ -1818,7 +1820,7 @@ index e52f9b06dd9c..182112fd845a 100644 + } + } + -+ if (type = PNV_THREAD_WINKLE) { ++ if (type == PNV_THREAD_WINKLE) { + sprs.tscr = mfspr(SPRN_TSCR); + sprs.worc = mfspr(SPRN_WORC); + @@ -1847,9 +1849,9 @@ index e52f9b06dd9c..182112fd845a 100644 + *state += 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; + if ((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) + >> PNV_CORE_IDLE_WINKLE_COUNT_SHIFT -+ = threads_per_core) ++ == threads_per_core) + *state |= PNV_CORE_IDLE_THREAD_WINKLE_BITS; -+ WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) = 0); ++ WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); + } + + atomic_unlock_thread_idle(); @@ -1882,14 +1884,14 @@ index e52f9b06dd9c..182112fd845a 100644 + } + } + -+ if (unlikely((srr1 & SRR1_WAKEMASK_P8) = SRR1_WAKEHMI)) ++ if (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI)) + hmi_exception_realmode(NULL); + + if (likely((srr1 & SRR1_WAKESTATE) != SRR1_WS_HVLOSS)) { + if (unlikely(type != PNV_THREAD_NAP)) { + atomic_lock_thread_idle(); -+ if (type = PNV_THREAD_WINKLE) { -+ WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) = 0); ++ if (type == PNV_THREAD_WINKLE) { ++ WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); + *state -= 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; + *state &= ~(thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT); + } @@ -1899,13 +1901,13 @@ index e52f9b06dd9c..182112fd845a 100644 + } + + /* HV state loss */ -+ BUG_ON(type = PNV_THREAD_NAP); ++ BUG_ON(type == PNV_THREAD_NAP); + + atomic_lock_thread_idle(); + + full_winkle = false; -+ if (type = PNV_THREAD_WINKLE) { -+ WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) = 0); ++ if (type == PNV_THREAD_WINKLE) { ++ WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); + *state -= 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; + if (*state & (thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT)) { + *state &= ~(thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT); @@ -2207,7 +2209,7 @@ index e52f9b06dd9c..182112fd845a 100644 + mtspr(SPRN_MMCRA, mmcra); + } + -+ if (unlikely((srr1 & SRR1_WAKEMASK_P8) = SRR1_WAKEHMI)) ++ if (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI)) + hmi_exception_realmode(NULL); + + /* @@ -2505,7 +2507,7 @@ index e52f9b06dd9c..182112fd845a 100644 + struct paca_struct *p = paca_ptrs[cpu]; + + p->idle_state = 0; -+ if (cpu = cpu_first_thread_sibling(cpu)) ++ if (cpu == cpu_first_thread_sibling(cpu)) + p->idle_state = (1 << threads_per_core) - 1; + + if (!cpu_has_feature(CPU_FTR_ARCH_300)) { diff --git a/a/content_digest b/N1/content_digest index a148c5c..494c512 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,7 +1,7 @@ "ref\020190428114515.32683-1-npiggin@gmail.com\0" "From\0Nicholas Piggin <npiggin@gmail.com>\0" "Subject\0[PATCH v10 1/2] powerpc/64s: reimplement book3s idle code in C\0" - "Date\0Sun, 28 Apr 2019 11:45:14 +0000\0" + "Date\0Sun, 28 Apr 2019 21:45:14 +1000\0" "To\0linuxppc-dev@lists.ozlabs.org\0" "Cc\0Gautham R . Shenoy <ego@linux.vnet.ibm.com>" kvm-ppc@vger.kernel.org @@ -722,7 +722,7 @@ "- */\n" "-power_enter_stop:\n" "-/*\n" - "- * Check if we are executing the lite variant with ESL\303\254=0\n" + "- * Check if we are executing the lite variant with ESL=EC=0\n" "- */\n" "-\tandis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED\n" "-\tclrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */\n" @@ -765,7 +765,7 @@ "-\t * reason, so there is no point setting r12 to SRR1.\n" "-\t *\n" "-\t * Further, we clear r12 here, so that we don't accidentally enter the\n" - "-\t * HMI in pnv_wakeup_noloss() if the value of r12[42:45] = WAKE_HMI.\n" + "-\t * HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI.\n" "-\t */\n" "-\tli\tr12, 0\n" "-\tb \tpnv_wakeup_noloss\n" @@ -1173,8 +1173,8 @@ "-\t * {\n" "-\t * bool first_in_core, first_in_subcore;\n" "-\t *\n" - "-\t * first_in_core = (core_idle_state & IDLE_THREAD_BITS) = 0;\n" - "-\t * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) = 0;\n" + "-\t * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;\n" + "-\t * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;\n" "-\t *\n" "-\t * core_idle_state |= thread_in_core;\n" "-\t * }\n" @@ -1189,12 +1189,12 @@ "-\t * {\n" "-\t * bool first_in_core, first_in_subcore, winkle_state_lost;\n" "-\t *\n" - "-\t * first_in_core = (core_idle_state & IDLE_THREAD_BITS) = 0;\n" - "-\t * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) = 0;\n" + "-\t * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;\n" + "-\t * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;\n" "-\t *\n" "-\t * core_idle_state |= thread_in_core;\n" "-\t *\n" - "-\t * if ((core_idle_state & WINKLE_MASK) = (8 << WINKLE_COUNT_SIHFT))\n" + "-\t * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT))\n" "-\t * core_idle_state |= THREAD_WINKLE_BITS;\n" "-\t * core_idle_state -= 1 << WINKLE_COUNT_SHIFT;\n" "-\t *\n" @@ -1639,8 +1639,10 @@ "-\t\t\t * if available.\n" "-\t\t\t */\n" "-\t\t\tif (default_stop_found) {\n" - "-\t\t\t\tpnv_deepest_stop_psscr_val -\t\t\t\t\tpnv_default_stop_val;\n" - "-\t\t\t\tpnv_deepest_stop_psscr_mask -\t\t\t\t\tpnv_default_stop_mask;\n" + "-\t\t\t\tpnv_deepest_stop_psscr_val =\n" + "-\t\t\t\t\tpnv_default_stop_val;\n" + "-\t\t\t\tpnv_deepest_stop_psscr_mask =\n" + "-\t\t\t\t\tpnv_default_stop_mask;\n" "-\t\t\t\tpr_warn(\"cpuidle-powernv: Offlined CPUs will stop with psscr = 0x%016llx\\n\",\n" "-\t\t\t\t\tpnv_deepest_stop_psscr_val);\n" "-\t\t\t} else { /* Fallback to snooze loop for CPU-Hotplug */\n" @@ -1820,7 +1822,7 @@ "+\t\t*state &= ~thread;\n" "+\n" "+\t\tif (power7_fastsleep_workaround_entry) {\n" - "+\t\t\tif ((*state & core_thread_mask) = 0) {\n" + "+\t\t\tif ((*state & core_thread_mask) == 0) {\n" "+\t\t\t\trc = opal_config_cpu_idle_state(\n" "+\t\t\t\t\t\tOPAL_CONFIG_IDLE_FASTSLEEP,\n" "+\t\t\t\t\t\tOPAL_CONFIG_IDLE_APPLY);\n" @@ -1828,7 +1830,7 @@ "+\t\t\t}\n" "+\t\t}\n" "+\n" - "+\t\tif (type = PNV_THREAD_WINKLE) {\n" + "+\t\tif (type == PNV_THREAD_WINKLE) {\n" "+\t\t\tsprs.tscr\t= mfspr(SPRN_TSCR);\n" "+\t\t\tsprs.worc\t= mfspr(SPRN_WORC);\n" "+\n" @@ -1857,9 +1859,9 @@ "+\t\t\t*state += 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT;\n" "+\t\t\tif ((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS)\n" "+\t\t\t\t\t>> PNV_CORE_IDLE_WINKLE_COUNT_SHIFT\n" - "+\t\t\t\t\t= threads_per_core)\n" + "+\t\t\t\t\t== threads_per_core)\n" "+\t\t\t\t*state |= PNV_CORE_IDLE_THREAD_WINKLE_BITS;\n" - "+\t\t\tWARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) = 0);\n" + "+\t\t\tWARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0);\n" "+\t\t}\n" "+\n" "+\t\tatomic_unlock_thread_idle();\n" @@ -1892,14 +1894,14 @@ "+\t\t}\n" "+\t}\n" "+\n" - "+\tif (unlikely((srr1 & SRR1_WAKEMASK_P8) = SRR1_WAKEHMI))\n" + "+\tif (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI))\n" "+\t\thmi_exception_realmode(NULL);\n" "+\n" "+\tif (likely((srr1 & SRR1_WAKESTATE) != SRR1_WS_HVLOSS)) {\n" "+\t\tif (unlikely(type != PNV_THREAD_NAP)) {\n" "+\t\t\tatomic_lock_thread_idle();\n" - "+\t\t\tif (type = PNV_THREAD_WINKLE) {\n" - "+\t\t\t\tWARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) = 0);\n" + "+\t\t\tif (type == PNV_THREAD_WINKLE) {\n" + "+\t\t\t\tWARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0);\n" "+\t\t\t\t*state -= 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT;\n" "+\t\t\t\t*state &= ~(thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT);\n" "+\t\t\t}\n" @@ -1909,13 +1911,13 @@ "+\t}\n" "+\n" "+\t/* HV state loss */\n" - "+\tBUG_ON(type = PNV_THREAD_NAP);\n" + "+\tBUG_ON(type == PNV_THREAD_NAP);\n" "+\n" "+\tatomic_lock_thread_idle();\n" "+\n" "+\tfull_winkle = false;\n" - "+\tif (type = PNV_THREAD_WINKLE) {\n" - "+\t\tWARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) = 0);\n" + "+\tif (type == PNV_THREAD_WINKLE) {\n" + "+\t\tWARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0);\n" "+\t\t*state -= 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT;\n" "+\t\tif (*state & (thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT)) {\n" "+\t\t\t*state &= ~(thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT);\n" @@ -2217,7 +2219,7 @@ "+\t\tmtspr(SPRN_MMCRA, mmcra);\n" "+\t}\n" "+\n" - "+\tif (unlikely((srr1 & SRR1_WAKEMASK_P8) = SRR1_WAKEHMI))\n" + "+\tif (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI))\n" "+\t\thmi_exception_realmode(NULL);\n" "+\n" "+\t/*\n" @@ -2515,7 +2517,7 @@ "+\t\tstruct paca_struct *p = paca_ptrs[cpu];\n" "+\n" "+\t\tp->idle_state = 0;\n" - "+\t\tif (cpu = cpu_first_thread_sibling(cpu))\n" + "+\t\tif (cpu == cpu_first_thread_sibling(cpu))\n" "+\t\t\tp->idle_state = (1 << threads_per_core) - 1;\n" "+\n" "+\t\tif (!cpu_has_feature(CPU_FTR_ARCH_300)) {\n" @@ -2656,4 +2658,4 @@ "-- \n" 2.20.1 -bb17babef3388d6347bf9fecde27f457fff3a600f914014d5ebd56479a4d10cd +e897628fb74af786dacf255760e4852fe3c5c17996f75df5449b153f88612e6f
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