From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90D16C43219 for ; Tue, 30 Apr 2019 20:31:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5E0C52087B for ; Tue, 30 Apr 2019 20:31:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="u8lQ5raS" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5E0C52087B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ravnborg.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+u2AvQjKRsndEQL7C8RpCt+c0VFwaRXlTwo+BuYCiSk=; b=u8lQ5raSL9UFdw Q2jpyoQnvjha3oRKbBdhq5685NsnL/GN3iSkwNV6NiDKwRz/kGiEoCWk/g0ecSXZNs+K0uQ/L74Xe s9jIkhRgtud35Iod0Jsq2yGaUKtKyzbj9dCWbmENhLsQZGfFv3ibACT4E3lqkHr+bu4K/Mh5hjF6e BQLDixdQDRnDSoCd1hJgOcYpwCUb7m8EQrgBqZeIBIMZmqJq1U9uIZFT004zJU3jVyHc4weZx7JMc s7gbq/Mx7CHpC64ujkZJxIxlV+ZBwJNW2z2vuaJ5V4OWE6OyZuiRc4D/Wq4glBgCIAl05BkqB86vS 8zQfZmJVMBslfvruumUQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hLZPZ-0003xk-OZ; Tue, 30 Apr 2019 20:31:33 +0000 Received: from asavdk3.altibox.net ([109.247.116.14]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hLZPU-0003m3-FD for linux-arm-kernel@lists.infradead.org; Tue, 30 Apr 2019 20:31:31 +0000 Received: from ravnborg.org (unknown [158.248.194.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by asavdk3.altibox.net (Postfix) with ESMTPS id 1589620047; Tue, 30 Apr 2019 22:31:10 +0200 (CEST) Date: Tue, 30 Apr 2019 22:31:08 +0200 From: Sam Ravnborg To: Guido =?iso-8859-1?Q?G=FCnther?= Subject: Re: [PATCH v9 2/2] phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs Message-ID: <20190430203108.GA20545@ravnborg.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CMAE-Score: 0 X-CMAE-Analysis: v=2.3 cv=dqr19Wo4 c=1 sm=1 tr=0 a=UWs3HLbX/2nnQ3s7vZ42gw==:117 a=UWs3HLbX/2nnQ3s7vZ42gw==:17 a=jpOVt7BSZ2e4Z31A5e1TngXxSK0=:19 a=IkcTkHD0fZMA:10 a=PLGMnwU6pitjcMjhYOwA:9 a=QEXdDO2ut3YA:10 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190430_133128_880233_B36B4CCB X-CRM114-Status: GOOD ( 22.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Heiko Stuebner , Maxime Ripard , dri-devel@lists.freedesktop.org, Fabio Estevam , Abel Vesa , Kishon Vijay Abraham I , NXP Linux Team , Robert Chiras , Thierry Reding , devicetree@vger.kernel.org, Martin Blumenstingl , Sascha Hauer , Johan Hovold , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Pengutronix Kernel Team , Lucas Stach , Shawn Guo , Andreas =?iso-8859-1?Q?F=E4rber?= , Li Jun Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGkgR3VpZG8uCgpUb29rIGEgbG9vayBhdCB0aGlzLCBidXQgZmVlZGJhY2sgaXMgdHJpdmlhbCBh cwpJIGhhdmUgbm8gZXhwZXJpZW5jZSB3aXRoIFBIWXMgc28gdXNlIG9ubHkKdGhlIGZlZWRiYWNr IHlvdSBjb25zaWRlciByZWxldmFudC4KCglTYW0KCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGh5 L2ZyZWVzY2FsZS9waHktZnNsLWlteDgtbWlwaS1kcGh5LmMgYi9kcml2ZXJzL3BoeS9mcmVlc2Nh bGUvcGh5LWZzbC1pbXg4LW1pcGktZHBoeS5jCj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPiBpbmRl eCAwMDAwMDAwMDAwMDAuLmQ2YjVhZjBiMzM4MAo+IC0tLSAvZGV2L251bGwKPiArKysgYi9kcml2 ZXJzL3BoeS9mcmVlc2NhbGUvcGh5LWZzbC1pbXg4LW1pcGktZHBoeS5jCj4gQEAgLTAsMCArMSw1 MDYgQEAKPiArLy8gU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjArCj4gKy8qCj4gKyAq IENvcHlyaWdodCAyMDE3LDIwMTggTlhQCj4gKyAqIENvcHlyaWdodCAyMDE5IFB1cmlzbSBTUEMK PiArICovCj4gKwo+ICsKPiArLyogRFBIWSByZWdpc3RlcnMgKi8KPiArI2RlZmluZSBEUEhZX1BE X0RQSFkJCQkweDAwCj4gKyNkZWZpbmUgRFBIWV9NX1BSR19IU19QUkVQQVJFCQkweDA0Cj4gKyNk ZWZpbmUgRFBIWV9NQ19QUkdfSFNfUFJFUEFSRQkJMHgwOAo+ICsjZGVmaW5lIERQSFlfTV9QUkdf SFNfWkVSTwkJMHgwYwo+ICsjZGVmaW5lIERQSFlfTUNfUFJHX0hTX1pFUk8JCTB4MTAKPiArI2Rl ZmluZSBEUEhZX01fUFJHX0hTX1RSQUlMCQkweDE0Cj4gKyNkZWZpbmUgRFBIWV9NQ19QUkdfSFNf VFJBSUwJCTB4MTgKPiArI2RlZmluZSBEUEhZX1BEX1BMTAkJCTB4MWMKPiArI2RlZmluZSBEUEhZ X1RTVAkJCTB4MjAKPiArI2RlZmluZSBEUEhZX0NOCQkJCTB4MjQKPiArI2RlZmluZSBEUEhZX0NN CQkJCTB4MjgKPiArI2RlZmluZSBEUEhZX0NPCQkJCTB4MmMKPiArI2RlZmluZSBEUEhZX0xPQ0sJ CQkweDMwCj4gKyNkZWZpbmUgRFBIWV9MT0NLX0JZUAkJCTB4MzQKPiArI2RlZmluZSBEUEhZX1JF R19CWVBBU1NfUExMCQkweDRDCj4gKwo+ICsjZGVmaW5lIE1CUFMoeCkgKCh4KSAqIDEwMDAwMDAp Cj4gKwo+ICsjZGVmaW5lIERBVEFfUkFURV9NQVhfU1BFRUQgTUJQUygxNTAwKQo+ICsjZGVmaW5l IERBVEFfUkFURV9NSU5fU1BFRUQgTUJQUyg4MCkKPiArCj4gKyNkZWZpbmUgUExMX0xPQ0tfU0xF RVAgMTAKPiArI2RlZmluZSBQTExfTE9DS19USU1FT1VUIDEwMDAKPiArCj4gKyNkZWZpbmUgQ05f QlVGCTB4Y2I3YTg5YzAKPiArI2RlZmluZSBDT19CVUYJMHg2Mwo+ICsjZGVmaW5lIENNKHgpCSgJ CQkJXAo+ICsJCSgoeCkgPAkzMik/MHhlMHwoKHgpLTE2KSA6CVwKPiArCQkoKHgpIDwJNjQpPzB4 YzB8KCh4KS0zMikgOglcCj4gKwkJKCh4KSA8IDEyOCk/MHg4MHwoKHgpLTY0KSA6CVwKPiArCQko KHgpIC0gMTI4KSkKPiArI2RlZmluZSBDTih4KQkoKCh4KSA9PSAxKT8weDFmIDogKCgoQ05fQlVG KT4+KCh4KS0xKSkmMHgxZikpCj4gKyNkZWZpbmUgQ08oeCkJKChDT19CVUYpPj4oOC0oeCkpJjB4 MykKPiArCj4gKy8qIFBIWSBwb3dlciBvbiBpcyBhY3RpdmUgbG93ICovCj4gKyNkZWZpbmUgUFdS X09OCTAKPiArI2RlZmluZSBQV1JfT0ZGCTEKPiArCj4gK2VudW0gbWl4ZWxfZHBoeV9kZXZ0eXBl IHsKPiArCU1JWEVMX0lNWDhNUSwKPiArfTsKPiArCj4gK3N0cnVjdCBtaXhlbF9kcGh5X2RldmRh dGEgewo+ICsJdTggcmVnX3R4X3JjYWw7Cj4gKwl1OCByZWdfYXV0b19wZF9lbjsKPiArCXU4IHJl Z19yeGxwcnA7Cj4gKwl1OCByZWdfcnhjZHJwOwo+ICsJdTggcmVnX3J4aHNfc2V0dGxlOwo+ICt9 Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVjdCBtaXhlbF9kcGh5X2RldmRhdGEgbWl4ZWxfZHBo eV9kZXZkYXRhW10gPSB7Cj4gKwlbTUlYRUxfSU1YOE1RXSA9IHsKPiArCQkucmVnX3R4X3JjYWwg PSAweDM4LAo+ICsJCS5yZWdfYXV0b19wZF9lbiA9IDB4M2MsCj4gKwkJLnJlZ19yeGxwcnAgPSAw eDQwLAo+ICsJCS5yZWdfcnhjZHJwID0gMHg0NCwKPiArCQkucmVnX3J4aHNfc2V0dGxlID0gMHg0 OCwKPiArCX0sCj4gK307Cj4gKwo+ICtzdHJ1Y3QgbWl4ZWxfZHBoeV9jZmcgewo+ICsJLyogRFBI WSBQTEwgcGFyYW1ldGVycyAqLwo+ICsJdTMyIGNtOwo+ICsJdTMyIGNuOwo+ICsJdTMyIGNvOwo+ ICsJLyogRFBIWSByZWdpc3RlciB2YWx1ZXMgKi8KPiArCXU4IG1jX3ByZ19oc19wcmVwYXJlOwo+ ICsJdTggbV9wcmdfaHNfcHJlcGFyZTsKPiArCXU4IG1jX3ByZ19oc196ZXJvOwo+ICsJdTggbV9w cmdfaHNfemVybzsKPiArCXU4IG1jX3ByZ19oc190cmFpbDsKPiArCXU4IG1fcHJnX2hzX3RyYWls Owo+ICsJdTggcnhoc19zZXR0bGU7Cj4gK307Cj4gKwo+ICtzdHJ1Y3QgbWl4ZWxfZHBoeV9wcml2 IHsKPiArCXN0cnVjdCBtaXhlbF9kcGh5X2NmZyBjZmc7Cj4gKwlzdHJ1Y3QgcmVnbWFwICpyZWdz OwpJdCBpcyBhIGxpdHRsZSBjb25mdXNpbmcgdGhhdCB0aGUgcmVnbWFwIGlzIG5hbWVkIHJlZ3Mu CkFzIHJlZ3MgaW4gbWFueSBvdGhlciBjYXNlcyBpcyB1c2VkIGFzIG5hbWUgZm9yIHRoZSB2YXJp YWJsZQp3aXRoIHBvaW50ZXIgdG8gcmVnaXN0ZXJzLgpTZWUgZm9yIGV4YW1wbGUgY2FsbCB0byBk ZXZtX3JlZ21hcF9pbml0X21taW8oKQoKPiArCXN0cnVjdCBjbGsgKnBoeV9yZWZfY2xrOwo+ICsJ Y29uc3Qgc3RydWN0IG1peGVsX2RwaHlfZGV2ZGF0YSAqZGV2ZGF0YTsKPiArfTsKPiArCj4gK3N0 YXRpYyBjb25zdCBzdHJ1Y3QgcmVnbWFwX2NvbmZpZyBtaXhlbF9kcGh5X3JlZ21hcF9jb25maWcg PSB7Cj4gKwkucmVnX2JpdHMgPSA4LAo+ICsJLnZhbF9iaXRzID0gMzIsCj4gKwkucmVnX3N0cmlk ZSA9IDQsCj4gKwkubWF4X3JlZ2lzdGVyID0gRFBIWV9SRUdfQllQQVNTX1BMTCwKPiArCS5uYW1l ID0gIm1pcGktZHBoeSIsCj4gK307Cj4gKwo+ICtzdGF0aWMgaW50IHBoeV93cml0ZShzdHJ1Y3Qg cGh5ICpwaHksIHUzMiB2YWx1ZSwgdW5zaWduZWQgaW50IHJlZykKPiArewo+ICsJc3RydWN0IG1p eGVsX2RwaHlfcHJpdiAqcHJpdiA9IHBoeV9nZXRfZHJ2ZGF0YShwaHkpOwo+ICsJaW50IHJldDsK PiArCj4gKwlyZXQgPSByZWdtYXBfd3JpdGUocHJpdi0+cmVncywgcmVnLCB2YWx1ZSk7Cj4gKwlp ZiAocmV0IDwgMCkKPiArCQlkZXZfZXJyKCZwaHktPmRldiwgIkZhaWxlZCB0byB3cml0ZSBEUEhZ IHJlZyAlZDogJWQiLCByZWcsIHJldCk7Cj4gKwlyZXR1cm4gcmV0Owo+ICt9Cj4gKwo+ICsvKgo+ ICsgKiBGaW5kIGEgcmF0aW8gY2xvc2UgdG8gdGhlIGRlc2lyZWQgb25lIHVzaW5nIGNvbnRpbnVl ZCBmcmFjdGlvbgo+ICsgKiBhcHByb3hpbWF0aW9uIGVuZGluZyBlaXRoZXIgYXQgZXhhY3QgbWF0 Y2ggb3IgbWF4aW11bSBhbGxvd2VkCj4gKyAqIG5vbWluYXRvciwgZGVub21pbmF0b3IuCj4gKyAq Lwo+ICtzdGF0aWMgdm9pZCBnZXRfYmVzdF9yYXRpbyh1MzIgKnBudW0sIHUzMiAqcGRlbm9tLCB1 bnNpZ25lZCBpbnQgbWF4X24sCj4gKwkJCSAgIHVuc2lnbmVkIGludCBtYXhfZCkKPiArewpNYXli ZSB1c2UgdTMyIGZvciBhbGwgcGFyYW1ldGVycz8KVGhhdCB3b3VsZCBhbHNvIG1hdGNoIHVzYWdl IGJlbG93LgoKPiArCXUzMiBhID0gKnBudW07Cj4gKwl1MzIgYiA9ICpwZGVub207Cj4gKwl1MzIg YzsKPiArCXUzMiBuW10gPSB7MCwgMX07Cj4gKwl1MzIgZFtdID0gezEsIDB9Owo+ICsJdTMyIHdo b2xlOwo+ICsJdW5zaWduZWQgaW50IGkgPSAxOwo+ICsKPiArCXdoaWxlIChiKSB7Cj4gKwkJaSBe PSAxOwo+ICsJCXdob2xlID0gYSAvIGI7Cj4gKwkJbltpXSArPSAobltpIF4gMV0gKiB3aG9sZSk7 Cj4gKwkJZFtpXSArPSAoZFtpIF4gMV0gKiB3aG9sZSk7Cj4gKwkJaWYgKChuW2ldID4gbWF4X24p IHx8IChkW2ldID4gbWF4X2QpKSB7Cj4gKwkJCWkgXj0gMTsKPiArCQkJYnJlYWs7Cj4gKwkJfQo+ ICsJCWMgPSBhIC0gKGIgKiB3aG9sZSk7Cj4gKwkJYSA9IGI7Cj4gKwkJYiA9IGM7Cj4gKwl9Cj4g KwkqcG51bSA9IG5baV07Cj4gKwkqcGRlbm9tID0gZFtpXTsKPiArfQo+ICsKPiArc3RhdGljIGlu dCBtaXhlbF9kcGh5X2NvbmZpZ19mcm9tX29wdHMoc3RydWN0IHBoeSAqcGh5LAo+ICsJICAgICAg IHN0cnVjdCBwaHlfY29uZmlndXJlX29wdHNfbWlwaV9kcGh5ICpkcGh5X29wdHMsCj4gKwkgICAg ICAgc3RydWN0IG1peGVsX2RwaHlfY2ZnICpjZmcpCj4gK3sKPiArCXN0cnVjdCBtaXhlbF9kcGh5 X3ByaXYgKnByaXYgPSBkZXZfZ2V0X2RydmRhdGEocGh5LT5kZXYucGFyZW50KTsKPiArCXVuc2ln bmVkIGxvbmcgcmVmX2NsayA9IGNsa19nZXRfcmF0ZShwcml2LT5waHlfcmVmX2Nsayk7Cj4gKwl1 MzIgbHBfdCwgbnVtZXJhdG9yLCBkZW5vbWluYXRvcjsKPiArCXVuc2lnbmVkIGxvbmcgbG9uZyB0 bXA7Cj4gKwl1MzIgbjsKPiArCWludCBpOwo+ICsKPiArCWlmIChkcGh5X29wdHMtPmhzX2Nsa19y YXRlID4gREFUQV9SQVRFX01BWF9TUEVFRCB8fAo+ICsJICAgIGRwaHlfb3B0cy0+aHNfY2xrX3Jh dGUgPCBEQVRBX1JBVEVfTUlOX1NQRUVEKQo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsKPiArCW51 bWVyYXRvciA9IGRwaHlfb3B0cy0+aHNfY2xrX3JhdGU7Cj4gKwlkZW5vbWluYXRvciA9IHJlZl9j bGs7Cj4gKwlnZXRfYmVzdF9yYXRpbygmbnVtZXJhdG9yLCAmZGVub21pbmF0b3IsIDI1NSwgMjU2 KTsKPiArCWlmICghbnVtZXJhdG9yIHx8ICFkZW5vbWluYXRvcikgewo+ICsJCWRldl9lcnIoJnBo eS0+ZGV2LCAiSW52YWxpZCAlZC8lZCBmb3IgJWxkLyVsZFxuIiwKPiArCQkJbnVtZXJhdG9yLCBk ZW5vbWluYXRvciwKPiArCQkJZHBoeV9vcHRzLT5oc19jbGtfcmF0ZSwgcmVmX2Nsayk7Cj4gKwkJ cmV0dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ICsJd2hpbGUgKChudW1lcmF0b3IgPCAxNikgJiYg KGRlbm9taW5hdG9yIDw9IDEyOCkpIHsKPiArCQludW1lcmF0b3IgPDw9IDE7Cj4gKwkJZGVub21p bmF0b3IgPDw9IDE7Cj4gKwl9Cj4gKwkvKgo+ICsJICogQ00gcmFuZ2VzIGJldHdlZW4gMTYgYW5k IDI1NQo+ICsJICogQ04gcmFuZ2VzIGJldHdlZW4gMSBhbmQgMzIKPiArCSAqIENPIGlzIHBvd2Vy IG9mIDI6IDEsIDIsIDQsIDgKPiArCSAqLwo+ICsJaSA9IF9fZmZzKGRlbm9taW5hdG9yKTsKPiAr CWlmIChpID4gMykKPiArCQlpID0gMzsKPiArCWNmZy0+Y24gPSBkZW5vbWluYXRvciA+PiBpOwo+ ICsJY2ZnLT5jbyA9IDEgPDwgaTsKPiArCWNmZy0+Y20gPSBudW1lcmF0b3I7Cj4gKwo+ICsJaWYg KGNmZy0+Y20gPCAxNiB8fCBjZmctPmNtID4gMjU1IHx8Cj4gKwkgICAgY2ZnLT5jbiA8IDEgfHwg Y2ZnLT5jbiA+IDMyIHx8Cj4gKwkgICAgY2ZnLT5jbyA8IDEgfHwgY2ZnLT5jbyA+IDgpIHsKPiAr CQlkZXZfZXJyKCZwaHktPmRldiwgIkludmFsaWQgQ00vQ04vQ08gdmFsdWVzOiAldS8ldS8ldVxu IiwKPiArCQkJY2ZnLT5jbSwgY2ZnLT5jbiwgY2ZnLT5jbyk7Cj4gKwkJZGV2X2VycigmcGh5LT5k ZXYsICJmb3IgaHNfY2xrL3JlZl9jbGs9JWxkLyVsZCDiqbAgJWQvJWRcbiIsCkhtbSwgbXkgbXV0 dCBkb2VzIG5vdCBsaWtlIHRoaXMgc3ltYm9sPyAg4qmwIAoKPiArCj4gKwlwaHlfd3JpdGUocGh5 LCBQV1JfT04sIERQSFlfUERfUExMKTsKPiArCXJldCA9IHJlZ21hcF9yZWFkX3BvbGxfdGltZW91 dChwcml2LT5yZWdzLCBEUEhZX0xPQ0ssIGxvY2tlZCwKPiArCQkJCSAgICAgICBsb2NrZWQsIFBM TF9MT0NLX1NMRUVQLAo+ICsJCQkJICAgICAgIFBMTF9MT0NLX1RJTUVPVVQpOwo+ICsJaWYgKHJl dCA8IDApIHsKPiArCQlkZXZfZXJyKCZwaHktPmRldiwgIkNvdWxkIG5vdCBnZXQgRFBIWSBsb2Nr ICglZCkhXG4iLCByZXQpOwo+ICsJCWdvdG8gY2xvY2tfZGlzYWJsZTsKPiArCX0KPiArCXBoeV93 cml0ZShwaHksIFBXUl9PTiwgRFBIWV9QRF9EUEhZKTsKCkFyZSB0aGVuIG5vIG90aGVyIHRpbWlu ZyBjb25zdHJhaW5zIHRoYW4gdGhlIHBvbGwgb2YgRFBIWV9MT0NLPwpTb21lIHBhbmVsIChJIGtu b3cgdGhpcyBpcyBub3QgYSBwYW5lbCwgYnV0IGFteXdheSkgaGF2ZSBzb21lCnJpZGdpZCB0aW1p bmcgY29uc3RyYWlucyBhcm91bmQgcG93ZXIgT04vT0ZGLgoKPiArCj4gK01PRFVMRV9BVVRIT1Io Ik5YUCBTZW1pY29uZHVjdG9yIik7Cj4gK01PRFVMRV9ERVNDUklQVElPTigiTWl4ZWwgTUlQSS1E U0kgUEhZIGRyaXZlciIpOwoKPiArTU9EVUxFX0xJQ0VOU0UoIkdQTCB2MiIpOwpEb2VzIHRoaXMg bWF0Y2ggdGhlIFNQRFggdGFnPwoKIgo+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BM LTIuMCsKIgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18K bGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZy YWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGlu dXgtYXJtLWtlcm5lbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sam Ravnborg Subject: Re: [PATCH v9 2/2] phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs Date: Tue, 30 Apr 2019 22:31:08 +0200 Message-ID: <20190430203108.GA20545@ravnborg.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Guido =?iso-8859-1?Q?G=FCnther?= Cc: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Thierry Reding , Andreas =?iso-8859-1?Q?F=E4rber?= , Martin Blumenstingl , Heiko Stuebner , Johan Hovold , Lucas Stach , Abel Vesa , Li Jun , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, Robert List-Id: devicetree@vger.kernel.org Hi Guido. Took a look at this, but feedback is trivial as I have no experience with PHYs so use only the feedback you consider relevant. Sam > diff --git a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c > new file mode 100644 > index 000000000000..d6b5af0b3380 > --- /dev/null > +++ b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c > @@ -0,0 +1,506 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2017,2018 NXP > + * Copyright 2019 Purism SPC > + */ > + > + > +/* DPHY registers */ > +#define DPHY_PD_DPHY 0x00 > +#define DPHY_M_PRG_HS_PREPARE 0x04 > +#define DPHY_MC_PRG_HS_PREPARE 0x08 > +#define DPHY_M_PRG_HS_ZERO 0x0c > +#define DPHY_MC_PRG_HS_ZERO 0x10 > +#define DPHY_M_PRG_HS_TRAIL 0x14 > +#define DPHY_MC_PRG_HS_TRAIL 0x18 > +#define DPHY_PD_PLL 0x1c > +#define DPHY_TST 0x20 > +#define DPHY_CN 0x24 > +#define DPHY_CM 0x28 > +#define DPHY_CO 0x2c > +#define DPHY_LOCK 0x30 > +#define DPHY_LOCK_BYP 0x34 > +#define DPHY_REG_BYPASS_PLL 0x4C > + > +#define MBPS(x) ((x) * 1000000) > + > +#define DATA_RATE_MAX_SPEED MBPS(1500) > +#define DATA_RATE_MIN_SPEED MBPS(80) > + > +#define PLL_LOCK_SLEEP 10 > +#define PLL_LOCK_TIMEOUT 1000 > + > +#define CN_BUF 0xcb7a89c0 > +#define CO_BUF 0x63 > +#define CM(x) ( \ > + ((x) < 32)?0xe0|((x)-16) : \ > + ((x) < 64)?0xc0|((x)-32) : \ > + ((x) < 128)?0x80|((x)-64) : \ > + ((x) - 128)) > +#define CN(x) (((x) == 1)?0x1f : (((CN_BUF)>>((x)-1))&0x1f)) > +#define CO(x) ((CO_BUF)>>(8-(x))&0x3) > + > +/* PHY power on is active low */ > +#define PWR_ON 0 > +#define PWR_OFF 1 > + > +enum mixel_dphy_devtype { > + MIXEL_IMX8MQ, > +}; > + > +struct mixel_dphy_devdata { > + u8 reg_tx_rcal; > + u8 reg_auto_pd_en; > + u8 reg_rxlprp; > + u8 reg_rxcdrp; > + u8 reg_rxhs_settle; > +}; > + > +static const struct mixel_dphy_devdata mixel_dphy_devdata[] = { > + [MIXEL_IMX8MQ] = { > + .reg_tx_rcal = 0x38, > + .reg_auto_pd_en = 0x3c, > + .reg_rxlprp = 0x40, > + .reg_rxcdrp = 0x44, > + .reg_rxhs_settle = 0x48, > + }, > +}; > + > +struct mixel_dphy_cfg { > + /* DPHY PLL parameters */ > + u32 cm; > + u32 cn; > + u32 co; > + /* DPHY register values */ > + u8 mc_prg_hs_prepare; > + u8 m_prg_hs_prepare; > + u8 mc_prg_hs_zero; > + u8 m_prg_hs_zero; > + u8 mc_prg_hs_trail; > + u8 m_prg_hs_trail; > + u8 rxhs_settle; > +}; > + > +struct mixel_dphy_priv { > + struct mixel_dphy_cfg cfg; > + struct regmap *regs; It is a little confusing that the regmap is named regs. As regs in many other cases is used as name for the variable with pointer to registers. See for example call to devm_regmap_init_mmio() > + struct clk *phy_ref_clk; > + const struct mixel_dphy_devdata *devdata; > +}; > + > +static const struct regmap_config mixel_dphy_regmap_config = { > + .reg_bits = 8, > + .val_bits = 32, > + .reg_stride = 4, > + .max_register = DPHY_REG_BYPASS_PLL, > + .name = "mipi-dphy", > +}; > + > +static int phy_write(struct phy *phy, u32 value, unsigned int reg) > +{ > + struct mixel_dphy_priv *priv = phy_get_drvdata(phy); > + int ret; > + > + ret = regmap_write(priv->regs, reg, value); > + if (ret < 0) > + dev_err(&phy->dev, "Failed to write DPHY reg %d: %d", reg, ret); > + return ret; > +} > + > +/* > + * Find a ratio close to the desired one using continued fraction > + * approximation ending either at exact match or maximum allowed > + * nominator, denominator. > + */ > +static void get_best_ratio(u32 *pnum, u32 *pdenom, unsigned int max_n, > + unsigned int max_d) > +{ Maybe use u32 for all parameters? That would also match usage below. > + u32 a = *pnum; > + u32 b = *pdenom; > + u32 c; > + u32 n[] = {0, 1}; > + u32 d[] = {1, 0}; > + u32 whole; > + unsigned int i = 1; > + > + while (b) { > + i ^= 1; > + whole = a / b; > + n[i] += (n[i ^ 1] * whole); > + d[i] += (d[i ^ 1] * whole); > + if ((n[i] > max_n) || (d[i] > max_d)) { > + i ^= 1; > + break; > + } > + c = a - (b * whole); > + a = b; > + b = c; > + } > + *pnum = n[i]; > + *pdenom = d[i]; > +} > + > +static int mixel_dphy_config_from_opts(struct phy *phy, > + struct phy_configure_opts_mipi_dphy *dphy_opts, > + struct mixel_dphy_cfg *cfg) > +{ > + struct mixel_dphy_priv *priv = dev_get_drvdata(phy->dev.parent); > + unsigned long ref_clk = clk_get_rate(priv->phy_ref_clk); > + u32 lp_t, numerator, denominator; > + unsigned long long tmp; > + u32 n; > + int i; > + > + if (dphy_opts->hs_clk_rate > DATA_RATE_MAX_SPEED || > + dphy_opts->hs_clk_rate < DATA_RATE_MIN_SPEED) > + return -EINVAL; > + > + numerator = dphy_opts->hs_clk_rate; > + denominator = ref_clk; > + get_best_ratio(&numerator, &denominator, 255, 256); > + if (!numerator || !denominator) { > + dev_err(&phy->dev, "Invalid %d/%d for %ld/%ld\n", > + numerator, denominator, > + dphy_opts->hs_clk_rate, ref_clk); > + return -EINVAL; > + } > + > + while ((numerator < 16) && (denominator <= 128)) { > + numerator <<= 1; > + denominator <<= 1; > + } > + /* > + * CM ranges between 16 and 255 > + * CN ranges between 1 and 32 > + * CO is power of 2: 1, 2, 4, 8 > + */ > + i = __ffs(denominator); > + if (i > 3) > + i = 3; > + cfg->cn = denominator >> i; > + cfg->co = 1 << i; > + cfg->cm = numerator; > + > + if (cfg->cm < 16 || cfg->cm > 255 || > + cfg->cn < 1 || cfg->cn > 32 || > + cfg->co < 1 || cfg->co > 8) { > + dev_err(&phy->dev, "Invalid CM/CN/CO values: %u/%u/%u\n", > + cfg->cm, cfg->cn, cfg->co); > + dev_err(&phy->dev, "for hs_clk/ref_clk=%ld/%ld ⩰ %d/%d\n", Hmm, my mutt does not like this symbol? ⩰ > + > + phy_write(phy, PWR_ON, DPHY_PD_PLL); > + ret = regmap_read_poll_timeout(priv->regs, DPHY_LOCK, locked, > + locked, PLL_LOCK_SLEEP, > + PLL_LOCK_TIMEOUT); > + if (ret < 0) { > + dev_err(&phy->dev, "Could not get DPHY lock (%d)!\n", ret); > + goto clock_disable; > + } > + phy_write(phy, PWR_ON, DPHY_PD_DPHY); Are then no other timing constrains than the poll of DPHY_LOCK? Some panel (I know this is not a panel, but amyway) have some ridgid timing constrains around power ON/OFF. > + > +MODULE_AUTHOR("NXP Semiconductor"); > +MODULE_DESCRIPTION("Mixel MIPI-DSI PHY driver"); > +MODULE_LICENSE("GPL v2"); Does this match the SPDX tag? " > +// SPDX-License-Identifier: GPL-2.0+ " From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF280C43219 for ; Tue, 30 Apr 2019 20:31:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ABEDB2087B for ; Tue, 30 Apr 2019 20:31:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726930AbfD3UbY (ORCPT ); Tue, 30 Apr 2019 16:31:24 -0400 Received: from asavdk3.altibox.net ([109.247.116.14]:56229 "EHLO asavdk3.altibox.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726030AbfD3UbY (ORCPT ); Tue, 30 Apr 2019 16:31:24 -0400 Received: from ravnborg.org (unknown [158.248.194.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by asavdk3.altibox.net (Postfix) with ESMTPS id 1589620047; Tue, 30 Apr 2019 22:31:10 +0200 (CEST) Date: Tue, 30 Apr 2019 22:31:08 +0200 From: Sam Ravnborg To: Guido =?iso-8859-1?Q?G=FCnther?= Cc: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Thierry Reding , Andreas =?iso-8859-1?Q?F=E4rber?= , Martin Blumenstingl , Heiko Stuebner , Johan Hovold , Lucas Stach , Abel Vesa , Li Jun , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, Robert Chiras , Maxime Ripard Subject: Re: [PATCH v9 2/2] phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs Message-ID: <20190430203108.GA20545@ravnborg.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CMAE-Score: 0 X-CMAE-Analysis: v=2.3 cv=dqr19Wo4 c=1 sm=1 tr=0 a=UWs3HLbX/2nnQ3s7vZ42gw==:117 a=UWs3HLbX/2nnQ3s7vZ42gw==:17 a=jpOVt7BSZ2e4Z31A5e1TngXxSK0=:19 a=IkcTkHD0fZMA:10 a=PLGMnwU6pitjcMjhYOwA:9 a=QEXdDO2ut3YA:10 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Guido. Took a look at this, but feedback is trivial as I have no experience with PHYs so use only the feedback you consider relevant. Sam > diff --git a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c > new file mode 100644 > index 000000000000..d6b5af0b3380 > --- /dev/null > +++ b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c > @@ -0,0 +1,506 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2017,2018 NXP > + * Copyright 2019 Purism SPC > + */ > + > + > +/* DPHY registers */ > +#define DPHY_PD_DPHY 0x00 > +#define DPHY_M_PRG_HS_PREPARE 0x04 > +#define DPHY_MC_PRG_HS_PREPARE 0x08 > +#define DPHY_M_PRG_HS_ZERO 0x0c > +#define DPHY_MC_PRG_HS_ZERO 0x10 > +#define DPHY_M_PRG_HS_TRAIL 0x14 > +#define DPHY_MC_PRG_HS_TRAIL 0x18 > +#define DPHY_PD_PLL 0x1c > +#define DPHY_TST 0x20 > +#define DPHY_CN 0x24 > +#define DPHY_CM 0x28 > +#define DPHY_CO 0x2c > +#define DPHY_LOCK 0x30 > +#define DPHY_LOCK_BYP 0x34 > +#define DPHY_REG_BYPASS_PLL 0x4C > + > +#define MBPS(x) ((x) * 1000000) > + > +#define DATA_RATE_MAX_SPEED MBPS(1500) > +#define DATA_RATE_MIN_SPEED MBPS(80) > + > +#define PLL_LOCK_SLEEP 10 > +#define PLL_LOCK_TIMEOUT 1000 > + > +#define CN_BUF 0xcb7a89c0 > +#define CO_BUF 0x63 > +#define CM(x) ( \ > + ((x) < 32)?0xe0|((x)-16) : \ > + ((x) < 64)?0xc0|((x)-32) : \ > + ((x) < 128)?0x80|((x)-64) : \ > + ((x) - 128)) > +#define CN(x) (((x) == 1)?0x1f : (((CN_BUF)>>((x)-1))&0x1f)) > +#define CO(x) ((CO_BUF)>>(8-(x))&0x3) > + > +/* PHY power on is active low */ > +#define PWR_ON 0 > +#define PWR_OFF 1 > + > +enum mixel_dphy_devtype { > + MIXEL_IMX8MQ, > +}; > + > +struct mixel_dphy_devdata { > + u8 reg_tx_rcal; > + u8 reg_auto_pd_en; > + u8 reg_rxlprp; > + u8 reg_rxcdrp; > + u8 reg_rxhs_settle; > +}; > + > +static const struct mixel_dphy_devdata mixel_dphy_devdata[] = { > + [MIXEL_IMX8MQ] = { > + .reg_tx_rcal = 0x38, > + .reg_auto_pd_en = 0x3c, > + .reg_rxlprp = 0x40, > + .reg_rxcdrp = 0x44, > + .reg_rxhs_settle = 0x48, > + }, > +}; > + > +struct mixel_dphy_cfg { > + /* DPHY PLL parameters */ > + u32 cm; > + u32 cn; > + u32 co; > + /* DPHY register values */ > + u8 mc_prg_hs_prepare; > + u8 m_prg_hs_prepare; > + u8 mc_prg_hs_zero; > + u8 m_prg_hs_zero; > + u8 mc_prg_hs_trail; > + u8 m_prg_hs_trail; > + u8 rxhs_settle; > +}; > + > +struct mixel_dphy_priv { > + struct mixel_dphy_cfg cfg; > + struct regmap *regs; It is a little confusing that the regmap is named regs. As regs in many other cases is used as name for the variable with pointer to registers. See for example call to devm_regmap_init_mmio() > + struct clk *phy_ref_clk; > + const struct mixel_dphy_devdata *devdata; > +}; > + > +static const struct regmap_config mixel_dphy_regmap_config = { > + .reg_bits = 8, > + .val_bits = 32, > + .reg_stride = 4, > + .max_register = DPHY_REG_BYPASS_PLL, > + .name = "mipi-dphy", > +}; > + > +static int phy_write(struct phy *phy, u32 value, unsigned int reg) > +{ > + struct mixel_dphy_priv *priv = phy_get_drvdata(phy); > + int ret; > + > + ret = regmap_write(priv->regs, reg, value); > + if (ret < 0) > + dev_err(&phy->dev, "Failed to write DPHY reg %d: %d", reg, ret); > + return ret; > +} > + > +/* > + * Find a ratio close to the desired one using continued fraction > + * approximation ending either at exact match or maximum allowed > + * nominator, denominator. > + */ > +static void get_best_ratio(u32 *pnum, u32 *pdenom, unsigned int max_n, > + unsigned int max_d) > +{ Maybe use u32 for all parameters? That would also match usage below. > + u32 a = *pnum; > + u32 b = *pdenom; > + u32 c; > + u32 n[] = {0, 1}; > + u32 d[] = {1, 0}; > + u32 whole; > + unsigned int i = 1; > + > + while (b) { > + i ^= 1; > + whole = a / b; > + n[i] += (n[i ^ 1] * whole); > + d[i] += (d[i ^ 1] * whole); > + if ((n[i] > max_n) || (d[i] > max_d)) { > + i ^= 1; > + break; > + } > + c = a - (b * whole); > + a = b; > + b = c; > + } > + *pnum = n[i]; > + *pdenom = d[i]; > +} > + > +static int mixel_dphy_config_from_opts(struct phy *phy, > + struct phy_configure_opts_mipi_dphy *dphy_opts, > + struct mixel_dphy_cfg *cfg) > +{ > + struct mixel_dphy_priv *priv = dev_get_drvdata(phy->dev.parent); > + unsigned long ref_clk = clk_get_rate(priv->phy_ref_clk); > + u32 lp_t, numerator, denominator; > + unsigned long long tmp; > + u32 n; > + int i; > + > + if (dphy_opts->hs_clk_rate > DATA_RATE_MAX_SPEED || > + dphy_opts->hs_clk_rate < DATA_RATE_MIN_SPEED) > + return -EINVAL; > + > + numerator = dphy_opts->hs_clk_rate; > + denominator = ref_clk; > + get_best_ratio(&numerator, &denominator, 255, 256); > + if (!numerator || !denominator) { > + dev_err(&phy->dev, "Invalid %d/%d for %ld/%ld\n", > + numerator, denominator, > + dphy_opts->hs_clk_rate, ref_clk); > + return -EINVAL; > + } > + > + while ((numerator < 16) && (denominator <= 128)) { > + numerator <<= 1; > + denominator <<= 1; > + } > + /* > + * CM ranges between 16 and 255 > + * CN ranges between 1 and 32 > + * CO is power of 2: 1, 2, 4, 8 > + */ > + i = __ffs(denominator); > + if (i > 3) > + i = 3; > + cfg->cn = denominator >> i; > + cfg->co = 1 << i; > + cfg->cm = numerator; > + > + if (cfg->cm < 16 || cfg->cm > 255 || > + cfg->cn < 1 || cfg->cn > 32 || > + cfg->co < 1 || cfg->co > 8) { > + dev_err(&phy->dev, "Invalid CM/CN/CO values: %u/%u/%u\n", > + cfg->cm, cfg->cn, cfg->co); > + dev_err(&phy->dev, "for hs_clk/ref_clk=%ld/%ld ⩰ %d/%d\n", Hmm, my mutt does not like this symbol? ⩰ > + > + phy_write(phy, PWR_ON, DPHY_PD_PLL); > + ret = regmap_read_poll_timeout(priv->regs, DPHY_LOCK, locked, > + locked, PLL_LOCK_SLEEP, > + PLL_LOCK_TIMEOUT); > + if (ret < 0) { > + dev_err(&phy->dev, "Could not get DPHY lock (%d)!\n", ret); > + goto clock_disable; > + } > + phy_write(phy, PWR_ON, DPHY_PD_DPHY); Are then no other timing constrains than the poll of DPHY_LOCK? Some panel (I know this is not a panel, but amyway) have some ridgid timing constrains around power ON/OFF. > + > +MODULE_AUTHOR("NXP Semiconductor"); > +MODULE_DESCRIPTION("Mixel MIPI-DSI PHY driver"); > +MODULE_LICENSE("GPL v2"); Does this match the SPDX tag? " > +// SPDX-License-Identifier: GPL-2.0+ "