From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sasha Levin Subject: [PATCH AUTOSEL 4.19 53/81] gpu: ipu-v3: dp: fix CSC handling Date: Tue, 7 May 2019 01:35:24 -0400 Message-ID: <20190507053554.30848-53-sashal@kernel.org> References: <20190507053554.30848-1-sashal@kernel.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id BEB7F89D40 for ; Tue, 7 May 2019 05:37:37 +0000 (UTC) In-Reply-To: <20190507053554.30848-1-sashal@kernel.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Sasha Levin , dri-devel@lists.freedesktop.org, Jonathan Marek List-Id: dri-devel@lists.freedesktop.org RnJvbTogTHVjYXMgU3RhY2ggPGwuc3RhY2hAcGVuZ3V0cm9uaXguZGU+CgpbIFVwc3RyZWFtIGNv bW1pdCBkNGZhZDBhNDI2YzZlMjZmNDhjOWE3Y2RkMjFhN2ZlOWMxOThkNjQ1IF0KCkluaXRpYWxp emUgdGhlIGZsb3cgaW5wdXQgY29sb3JzcGFjZXMgdG8gdW5rbm93biBhbmQgcmVzZXQgdG8gdGhh dCB2YWx1ZQp3aGVuIHRoZSBjaGFubmVsIGdldHMgZGlzYWJsZWQuIFRoaXMgYXZvaWRzIHRoZSBz dGF0ZSBnZXR0aW5nIG1peGVkIHVwCndpdGggYSBwcmV2aW91cyBtb2RlLgoKQWxzbyBrZWVwIHRo ZSBDU0Mgc2V0dGluZ3MgZm9yIHRoZSBiYWNrZ3JvdW5kIGZsb3cgaW50YWN0IHdoZW4gZGlzYWJs aW5nCnRoZSBmb3JlZ3JvdW5kIGZsb3cuCgpSb290LWNhdXNlZC1ieTogSm9uYXRoYW4gTWFyZWsg PGpvbmF0aGFuQG1hcmVrLmNhPgpTaWduZWQtb2ZmLWJ5OiBMdWNhcyBTdGFjaCA8bC5zdGFjaEBw ZW5ndXRyb25peC5kZT4KU2lnbmVkLW9mZi1ieTogUGhpbGlwcCBaYWJlbCA8cC56YWJlbEBwZW5n dXRyb25peC5kZT4KU2lnbmVkLW9mZi1ieTogU2FzaGEgTGV2aW4gPHNhc2hhbEBrZXJuZWwub3Jn PgotLS0KIGRyaXZlcnMvZ3B1L2lwdS12My9pcHUtZHAuYyB8IDEyICsrKysrKysrKy0tLQogMSBm aWxlIGNoYW5nZWQsIDkgaW5zZXJ0aW9ucygrKSwgMyBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQg YS9kcml2ZXJzL2dwdS9pcHUtdjMvaXB1LWRwLmMgYi9kcml2ZXJzL2dwdS9pcHUtdjMvaXB1LWRw LmMKaW5kZXggOWIyYjNmYTQ3OWM0Li41ZTQ0ZmYxZjIwODUgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMv Z3B1L2lwdS12My9pcHUtZHAuYworKysgYi9kcml2ZXJzL2dwdS9pcHUtdjMvaXB1LWRwLmMKQEAg LTE5NSw3ICsxOTUsOCBAQCBpbnQgaXB1X2RwX3NldHVwX2NoYW5uZWwoc3RydWN0IGlwdV9kcCAq ZHAsCiAJCWlwdV9kcF9jc2NfaW5pdChmbG93LCBmbG93LT5mb3JlZ3JvdW5kLmluX2NzLCBmbG93 LT5vdXRfY3MsCiAJCQkJRFBfQ09NX0NPTkZfQ1NDX0RFRl9CT1RIKTsKIAl9IGVsc2UgewotCQlp ZiAoZmxvdy0+Zm9yZWdyb3VuZC5pbl9jcyA9PSBmbG93LT5vdXRfY3MpCisJCWlmIChmbG93LT5m b3JlZ3JvdW5kLmluX2NzID09IElQVVYzX0NPTE9SU1BBQ0VfVU5LTk9XTiB8fAorCQkgICAgZmxv dy0+Zm9yZWdyb3VuZC5pbl9jcyA9PSBmbG93LT5vdXRfY3MpCiAJCQkvKgogCQkJICogZm9yZWdy b3VuZCBpZGVudGljYWwgdG8gb3V0cHV0LCBhcHBseSBjb2xvcgogCQkJICogY29udmVyc2lvbiBv biBiYWNrZ3JvdW5kCkBAIC0yNjEsNiArMjYyLDggQEAgdm9pZCBpcHVfZHBfZGlzYWJsZV9jaGFu bmVsKHN0cnVjdCBpcHVfZHAgKmRwLCBib29sIHN5bmMpCiAJc3RydWN0IGlwdV9kcF9wcml2ICpw cml2ID0gZmxvdy0+cHJpdjsKIAl1MzIgcmVnLCBjc2M7CiAKKwlkcC0+aW5fY3MgPSBJUFVWM19D T0xPUlNQQUNFX1VOS05PV047CisKIAlpZiAoIWRwLT5mb3JlZ3JvdW5kKQogCQlyZXR1cm47CiAK QEAgLTI2OCw4ICsyNzEsOSBAQCB2b2lkIGlwdV9kcF9kaXNhYmxlX2NoYW5uZWwoc3RydWN0IGlw dV9kcCAqZHAsIGJvb2wgc3luYykKIAogCXJlZyA9IHJlYWRsKGZsb3ctPmJhc2UgKyBEUF9DT01f Q09ORik7CiAJY3NjID0gcmVnICYgRFBfQ09NX0NPTkZfQ1NDX0RFRl9NQVNLOwotCWlmIChjc2Mg PT0gRFBfQ09NX0NPTkZfQ1NDX0RFRl9GRykKLQkJcmVnICY9IH5EUF9DT01fQ09ORl9DU0NfREVG X01BU0s7CisJcmVnICY9IH5EUF9DT01fQ09ORl9DU0NfREVGX01BU0s7CisJaWYgKGNzYyA9PSBE UF9DT01fQ09ORl9DU0NfREVGX0JPVEggfHwgY3NjID09IERQX0NPTV9DT05GX0NTQ19ERUZfQkcp CisJCXJlZyB8PSBEUF9DT01fQ09ORl9DU0NfREVGX0JHOwogCiAJcmVnICY9IH5EUF9DT01fQ09O Rl9GR19FTjsKIAl3cml0ZWwocmVnLCBmbG93LT5iYXNlICsgRFBfQ09NX0NPTkYpOwpAQCAtMzQ3 LDYgKzM1MSw4IEBAIGludCBpcHVfZHBfaW5pdChzdHJ1Y3QgaXB1X3NvYyAqaXB1LCBzdHJ1Y3Qg ZGV2aWNlICpkZXYsIHVuc2lnbmVkIGxvbmcgYmFzZSkKIAltdXRleF9pbml0KCZwcml2LT5tdXRl eCk7CiAKIAlmb3IgKGkgPSAwOyBpIDwgSVBVVjNfTlVNX0ZMT1dTOyBpKyspIHsKKwkJcHJpdi0+ Zmxvd1tpXS5iYWNrZ3JvdW5kLmluX2NzID0gSVBVVjNfQ09MT1JTUEFDRV9VTktOT1dOOworCQlw cml2LT5mbG93W2ldLmZvcmVncm91bmQuaW5fY3MgPSBJUFVWM19DT0xPUlNQQUNFX1VOS05PV047 CiAJCXByaXYtPmZsb3dbaV0uZm9yZWdyb3VuZC5mb3JlZ3JvdW5kID0gdHJ1ZTsKIAkJcHJpdi0+ Zmxvd1tpXS5iYXNlID0gcHJpdi0+YmFzZSArIGlwdV9kcF9mbG93X2Jhc2VbaV07CiAJCXByaXYt PmZsb3dbaV0ucHJpdiA9IHByaXY7Ci0tIAoyLjIwLjEKCl9fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVs QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWls bWFuL2xpc3RpbmZvL2RyaS1kZXZlbA== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS, T_DKIMWL_WL_HIGH,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5EBAC004C9 for ; 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Tue, 7 May 2019 05:37:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1557207457; bh=1a82mOvcxiOhSPOIhzwEn0QxH4OostE6OsD7NBGsYhg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XMZHawQtnVp0yjXAK0/wtZBl+tLVnqLdcuZ1xSSk8fLwT0Zhz8u1hKNis3xAKdcdy /JODburk/crQgfTpLsetHbrfi431vQFg99oKRXWdvh/AzXa2EwJhXjctZo2In+phwg vEtwjBxXbWNb2W2GMaOpwq/E3OWL0HCWgzLUHM7A= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Lucas Stach , Jonathan Marek , Philipp Zabel , Sasha Levin , dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 4.19 53/81] gpu: ipu-v3: dp: fix CSC handling Date: Tue, 7 May 2019 01:35:24 -0400 Message-Id: <20190507053554.30848-53-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507053554.30848-1-sashal@kernel.org> References: <20190507053554.30848-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Lucas Stach [ Upstream commit d4fad0a426c6e26f48c9a7cdd21a7fe9c198d645 ] Initialize the flow input colorspaces to unknown and reset to that value when the channel gets disabled. This avoids the state getting mixed up with a previous mode. Also keep the CSC settings for the background flow intact when disabling the foreground flow. Root-caused-by: Jonathan Marek Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel Signed-off-by: Sasha Levin --- drivers/gpu/ipu-v3/ipu-dp.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/ipu-v3/ipu-dp.c b/drivers/gpu/ipu-v3/ipu-dp.c index 9b2b3fa479c4..5e44ff1f2085 100644 --- a/drivers/gpu/ipu-v3/ipu-dp.c +++ b/drivers/gpu/ipu-v3/ipu-dp.c @@ -195,7 +195,8 @@ int ipu_dp_setup_channel(struct ipu_dp *dp, ipu_dp_csc_init(flow, flow->foreground.in_cs, flow->out_cs, DP_COM_CONF_CSC_DEF_BOTH); } else { - if (flow->foreground.in_cs == flow->out_cs) + if (flow->foreground.in_cs == IPUV3_COLORSPACE_UNKNOWN || + flow->foreground.in_cs == flow->out_cs) /* * foreground identical to output, apply color * conversion on background @@ -261,6 +262,8 @@ void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync) struct ipu_dp_priv *priv = flow->priv; u32 reg, csc; + dp->in_cs = IPUV3_COLORSPACE_UNKNOWN; + if (!dp->foreground) return; @@ -268,8 +271,9 @@ void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync) reg = readl(flow->base + DP_COM_CONF); csc = reg & DP_COM_CONF_CSC_DEF_MASK; - if (csc == DP_COM_CONF_CSC_DEF_FG) - reg &= ~DP_COM_CONF_CSC_DEF_MASK; + reg &= ~DP_COM_CONF_CSC_DEF_MASK; + if (csc == DP_COM_CONF_CSC_DEF_BOTH || csc == DP_COM_CONF_CSC_DEF_BG) + reg |= DP_COM_CONF_CSC_DEF_BG; reg &= ~DP_COM_CONF_FG_EN; writel(reg, flow->base + DP_COM_CONF); @@ -347,6 +351,8 @@ int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base) mutex_init(&priv->mutex); for (i = 0; i < IPUV3_NUM_FLOWS; i++) { + priv->flow[i].background.in_cs = IPUV3_COLORSPACE_UNKNOWN; + priv->flow[i].foreground.in_cs = IPUV3_COLORSPACE_UNKNOWN; priv->flow[i].foreground.foreground = true; priv->flow[i].base = priv->base + ipu_dp_flow_base[i]; priv->flow[i].priv = priv; -- 2.20.1