[U-Boot] [PATCH] Revert "mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue"

[Lukasz Majewski <lukma@denx.de>]

Hi Peng,

> Hi Lukasz,
> 
> > Subject: [PATCH] Revert "mmc: fsl_esdhc: fix sd/mmc ddr mode clock
> > setting issue"
> > 
> > This reverts commit 72a89e0da5ac6a4ab929b15a2b656f04f50767f6, which
> > causes the imx53 HSC to hang as the eMMC is not working properly
> > anymore.
> > 
> > The exact error message:
> > MMC write: dev # 0, block # 2, count 927 ... mmc write failed
> > 0 blocks written: ERROR
> > 
> > imx53 is not using the DDR mode.
> > 
> > Debugging of pre_div and div generation showed that those values are
> > generated in a way, which is not matching the ones from working
> > setup.
> > 
> > As the original patch was performing code refactoring, let's revert
> > this change, so all imx53 boards would work again.  
> 
> Could you share what is the clock value for your board?

Sure, no problem:

Working setup:
--------------

MMC:
set_sysctl: pre_div = 2 mmc->ddr: 0 sdhc_clk: 80000000
 pre_div: 8 div: 12 set_sysctl: clk: 2240
FSL_SDHC: 0
Loading Environment from MMC...
set_sysctl: pre_div = 2 mmc->ddr: 0 sdhc_clk: 80000000
 pre_div: 8 div: 12 set_sysctl: clk: 2240

set_sysctl: pre_div = 2 mmc->ddr: 0 sdhc_clk: 80000000
 pre_div: 8 div: 12 set_sysctl: clk: 2240

set_sysctl: pre_div = 2 mmc->ddr: 0 sdhc_clk: 80000000
 pre_div: 1 div: 1 set_sysctl: clk: 272

set_sysctl: pre_div = 2 mmc->ddr: 0 sdhc_clk: 80000000
 pre_div: 1 div: 0 set_sysctl: clk: 256




Broken:
-------
MMC:
set_sysctl: pre_div = 2 mmc->ddr: 0 sdhc_clk: 80000000
 pre_div: 8 div: 12 set_sysctl: clk: 2240
FSL_SDHC: 0
Loading Environment from MMC...
set_sysctl: pre_div = 2 mmc->ddr: 0 sdhc_clk: 80000000
 pre_div: 8 div: 12 set_sysctl: clk: 2240

set_sysctl: pre_div = 2 mmc->ddr: 0 sdhc_clk: 80000000
 pre_div: 8 div: 12 set_sysctl: clk: 2240

set_sysctl: pre_div = 2 mmc->ddr: 0 sdhc_clk: 80000000
 pre_div: 0 div: 3 set_sysctl: clk: 48

set_sysctl: pre_div = 2 mmc->ddr: 0 sdhc_clk: 80000000
 pre_div: 0 div: 1 set_sysctl: clk: 16


(Please also find attached patch to reproduce debug output).

> 
> Thanks,
> Peng.
> 
> > 
> > Signed-off-by: Lukasz Majewski <lukma@denx.de>
> > ---
> >  drivers/mmc/fsl_esdhc.c | 23 +++++------------------
> >  1 file changed, 5 insertions(+), 18 deletions(-)
> > 
> > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index
> > 1b7de74a72..377b2673a3 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc.c
> > @@ -621,31 +621,18 @@ static void set_sysctl(struct fsl_esdhc_priv
> > *priv, struct mmc *mmc, uint clock)  #else
> >  	int pre_div = 2;
> >  #endif
> > +	int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
> >  	int sdhc_clk = priv->sdhc_clk;
> >  	uint clk;
> > 
> > -	/*
> > -	 * For ddr mode, usdhc need to enable DDR mode first,
> > after select
> > -	 * this DDR mode, usdhc will automatically divide the
> > usdhc clock
> > -	 */
> > -	if (mmc->ddr_mode) {
> > -		writel(readl(&regs->mixctrl) | MIX_CTRL_DDREN,
> > &regs->mixctrl);
> > -		sdhc_clk >>= 1;
> > -	}
> > -
> >  	if (clock < mmc->cfg->f_min)
> >  		clock = mmc->cfg->f_min;
> > 
> > -	if (sdhc_clk / 16 > clock) {
> > -		for (; pre_div < 256; pre_div *= 2)
> > -			if ((sdhc_clk / pre_div) <= (clock * 16))
> > -				break;
> > -	} else
> > -		pre_div = 1;
> > +	while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock &&
> > pre_div < 256)
> > +		pre_div *= 2;
> > 
> > -	for (div = 1; div <= 16; div++)
> > -		if ((sdhc_clk / (div * pre_div)) <= clock)
> > -			break;
> > +	while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock &&
> > div < 16)
> > +		div++;
> > 
> >  	pre_div >>= 1;
> >  	div -= 1;
> > --
> > 2.11.0  
> 




Best regards,

Lukasz Majewski

--

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