From: "Daniel P. Berrangé" <berrange@redhat.com>
To: Tao Xu <tao3.xu@intel.com>
Cc: ehabkost@redhat.com, xiaoyao.li@intel.com, qemu-devel@nongnu.org,
robert.hu@intel.com, pbonzini@redhat.com, rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH v3] i386: Add some MSR based features on Cascadelake-Server CPU model
Date: Wed, 8 May 2019 10:12:13 +0100 [thread overview]
Message-ID: <20190508091213.GC32552@redhat.com> (raw)
In-Reply-To: <20190508013153.15412-1-tao3.xu@intel.com>
On Wed, May 08, 2019 at 09:31:53AM +0800, Tao Xu wrote:
> As noted in "c7a88b52f6 i386: Add new model of Cascadelake-Server"
> Because MSR based feature has been supported by QEMU, we add
> CPUID_7_0_EDX_ARCH_CAPABILITIES on Cascadelake-Server CPU model,
> and add IA32_ARCH_CAPABILITIES MSR based features (RDCL_NO,
> IBRS_ALL and SKIP_L1DFL_VMENTRY).
>
> And "014018e19b i386: Make arch_capabilities migratable" has been
> in QEMU upstream, the CPUID_7_0_EDX_ARCH_CAPABILITIES can be
> safely added into CPU Model.
>
> Signed-off-by: Tao Xu <tao3.xu@intel.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Regards,
Daniel
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next prev parent reply other threads:[~2019-05-08 9:13 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-08 1:31 [Qemu-devel] [PATCH v3] i386: Add some MSR based features on Cascadelake-Server CPU model Tao Xu
2019-05-08 9:12 ` Daniel P. Berrangé [this message]
2019-05-08 20:01 ` Eduardo Habkost
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