From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33C9DC04AA7 for ; Mon, 13 May 2019 18:08:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 01A9A2086A for ; Mon, 13 May 2019 18:08:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="rUGz5Miu" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731485AbfEMSIF (ORCPT ); Mon, 13 May 2019 14:08:05 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3090 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731142AbfEMSIF (ORCPT ); Mon, 13 May 2019 14:08:05 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 13 May 2019 11:07:25 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 13 May 2019 11:08:04 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 13 May 2019 11:08:04 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 13 May 2019 18:08:04 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 13 May 2019 18:08:00 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 01/29] soc/tegra: pmc: Export tegra_powergate_power_on() Date: Mon, 13 May 2019 23:37:16 +0530 Message-ID: <20190513180744.16493-2-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190513180744.16493-1-mmaddireddy@nvidia.com> References: <20190513180744.16493-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557770845; bh=44xf+nRMDS/qkjpmAuRx/TmLE+5nvwmcHGE9hv0QivY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=rUGz5MiuZENBRk8UIEHjyl7bnT5s4AbRlHGRIP3nO676dCcuPfOV7rWgZVyj5Th8q 0qqaPNWEb7d609VgCRDJ51l0T+bWdr6rEqC84LfP9MtPZzYHj89vI0qZI99aroyA7W fVBkTx5XaFI7QbLbogX33LZuK+iosSqkaOPsiA3DQv6TywmTuQJwqPtllnhoPLtpm2 cmmj6esq3jAOTmrE4BzEcLQueT2zgepe2qYyA5+f91OTaXjw4QqjdH+m6tbbTIIIqy wMZEFPOPkIC7KUM+0+e4YzV5ZdsLDcNQQ3euGsdXO3xzuXtv/CAqIGUAUNDKlu/Dh6 svg6dcvtMj9DA== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org tegra_powergate_sequence_power_up() powers up partition and also enables clock & reset. However, if a controller like PCIe have multiple clocks & resets and they need to be enabled in a sequence, driver must use standalone function tegra_powergate_power_on() to power up partition. Export tegra_powergate_power_on() to allow Tegra controller drivers to unpower gate partition independent to clock & reset. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V3: No change V2: No change drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 0c5f79528e5f..cb3de81348bd 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -701,6 +701,7 @@ int tegra_powergate_power_on(unsigned int id) return tegra_powergate_set(pmc, id, true); } +EXPORT_SYMBOL(tegra_powergate_power_on); /** * tegra_powergate_power_off() - power off partition -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Manikanta Maddireddy Subject: [PATCH V3 01/29] soc/tegra: pmc: Export tegra_powergate_power_on() Date: Mon, 13 May 2019 23:37:16 +0530 Message-ID: <20190513180744.16493-2-mmaddireddy@nvidia.com> In-Reply-To: <20190513180744.16493-1-mmaddireddy@nvidia.com> References: <20190513180744.16493-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain To: thierry.reding@gmail.com, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com, lorenzo.pieralisi@arm.com, vidyas@nvidia.com Cc: linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manikanta Maddireddy List-ID: tegra_powergate_sequence_power_up() powers up partition and also enables clock & reset. However, if a controller like PCIe have multiple clocks & resets and they need to be enabled in a sequence, driver must use standalone function tegra_powergate_power_on() to power up partition. Export tegra_powergate_power_on() to allow Tegra controller drivers to unpower gate partition independent to clock & reset. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V3: No change V2: No change drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 0c5f79528e5f..cb3de81348bd 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -701,6 +701,7 @@ int tegra_powergate_power_on(unsigned int id) return tegra_powergate_set(pmc, id, true); } +EXPORT_SYMBOL(tegra_powergate_power_on); /** * tegra_powergate_power_off() - power off partition -- 2.17.1