From: Borislav Petkov <bp@alien8.de>
To: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
Cc: "Luck, Tony" <tony.luck@intel.com>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH v3 5/6] x86/MCE: Save MCA control bits that get set in hardware
Date: Fri, 17 May 2019 22:02:25 +0200 [thread overview]
Message-ID: <20190517200225.GK13482@zn.tnic> (raw)
In-Reply-To: <SN6PR12MB2639C5427366AC3004C35CC0F80B0@SN6PR12MB2639.namprd12.prod.outlook.com>
On Fri, May 17, 2019 at 07:49:10PM +0000, Ghannam, Yazen wrote:
> > @@ -1569,7 +1575,13 @@ static void __mcheck_cpu_init_clear_banks(void)
> >
> > if (!b->init)
> > continue;
> > +
> > + /* Check if any bits are implemented in h/w */
> > wrmsrl(msr_ops.ctl(i), b->ctl);
> > + rdmsrl(msr_ops.ctl(i), msrval);
> > +
> > + b->init = !!msrval;
> > +
> Just a minor nit, but can we group the comment, RDMSR, and check
> together? The WRMSR is part of normal operation and isn't tied to the
> check.
Of course it is - that's the "throw all 1s at it" part :)
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
next prev parent reply other threads:[~2019-05-17 20:02 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-30 20:32 [PATCH v3 0/6] Handle MCA banks in a per_cpu way Ghannam, Yazen
2019-04-30 20:32 ` [v3,5/6] x86/MCE: Save MCA control bits that get set in hardware Yazen Ghannam
2019-04-30 20:32 ` [PATCH v3 5/6] " Ghannam, Yazen
2019-05-16 15:52 ` Luck, Tony
2019-05-16 16:14 ` Ghannam, Yazen
2019-05-16 16:56 ` Borislav Petkov
2019-05-16 17:09 ` Ghannam, Yazen
2019-05-16 17:21 ` Borislav Petkov
2019-05-16 20:20 ` Ghannam, Yazen
2019-05-16 20:34 ` Borislav Petkov
2019-05-16 20:59 ` Luck, Tony
2019-05-17 10:10 ` Borislav Petkov
2019-05-17 15:46 ` Ghannam, Yazen
2019-05-17 16:37 ` Borislav Petkov
2019-05-17 17:26 ` Luck, Tony
2019-05-17 17:48 ` Borislav Petkov
2019-05-17 18:06 ` Luck, Tony
2019-05-17 19:34 ` Borislav Petkov
2019-05-17 19:44 ` Luck, Tony
2019-05-17 19:50 ` Borislav Petkov
2019-05-17 19:49 ` Ghannam, Yazen
2019-05-17 20:02 ` Borislav Petkov [this message]
2019-05-23 20:00 ` Ghannam, Yazen
2019-05-27 23:28 ` Borislav Petkov
2019-06-07 14:49 ` Ghannam, Yazen
2019-06-07 16:37 ` Borislav Petkov
2019-06-07 16:44 ` Ghannam, Yazen
2019-06-07 16:59 ` Borislav Petkov
2019-06-07 17:08 ` Ghannam, Yazen
2019-06-07 17:20 ` Borislav Petkov
2019-06-11 5:13 ` Borislav Petkov
2019-04-30 20:32 ` [v3,4/6] x86/MCE: Make number of MCA banks per_cpu Yazen Ghannam
2019-04-30 20:32 ` [PATCH v3 4/6] " Ghannam, Yazen
2019-05-18 11:25 ` Borislav Petkov
2019-05-21 17:52 ` Ghannam, Yazen
2019-05-21 20:29 ` Borislav Petkov
2019-05-21 20:42 ` Luck, Tony
2019-05-21 23:09 ` Borislav Petkov
2019-05-22 14:01 ` Ghannam, Yazen
-- strict thread matches above, loose matches on Subject: below --
2019-04-30 20:32 [v3,6/6] x86/MCE: Treat MCE bank as initialized if control bits set in hardware Yazen Ghannam
2019-04-30 20:32 ` [PATCH v3 6/6] " Ghannam, Yazen
2019-04-30 20:32 [v3,3/6] x86/MCE/AMD: Don't cache block addresses on SMCA systems Yazen Ghannam
2019-04-30 20:32 ` [PATCH v3 3/6] " Ghannam, Yazen
2019-04-30 20:32 [v3,2/6] x86/MCE: Handle MCA controls in a per_cpu way Yazen Ghannam
2019-04-30 20:32 ` [PATCH v3 2/6] " Ghannam, Yazen
2019-04-30 20:32 [v3,1/6] x86/MCE: Make struct mce_banks[] static Yazen Ghannam
2019-04-30 20:32 ` [PATCH v3 1/6] " Ghannam, Yazen
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