From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76F10C04AAC for ; Mon, 20 May 2019 13:38:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 44F2920856 for ; Mon, 20 May 2019 13:38:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="BrWcc56l"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="Dkz9NX5I" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 44F2920856 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6OgtxzxszI4cDCg7auZQHe2m/3kfyVvHgSuoYdnWsmo=; b=BrWcc56lDFSOom CKg4Ho2t0mRjhQXg4XdTAyDjRTfbimG4WcSmjON2qfgIZKAUkaT8/847KDdceMXysbJAc+dpqHgQ8 VIK3H2toIV+mZTWgqyzqgua6Gh23iiv1UJLlDbdRh6fr8KIjyYBGNyi7VM5Ly6gApWez+YWGIECZS sbBLhPddU3lPtpHP53uL27tu+yeON+d3Mzkdf7bpy0PmkES1d1jR8rtBLTGCixw3+YearkMUKBaX0 mCg575IrMkOEb4sgXqVyaUft33lVbEB71wx90eQUJ+IeHl/L1epfE6HVBawEd916MQGC25Gvj3yZX W114gKJGtt4rNiCGQX+A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hSiUe-0005BD-Uv; Mon, 20 May 2019 13:38:21 +0000 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hSiUN-0004wq-1U for linux-amlogic@lists.infradead.org; Mon, 20 May 2019 13:38:05 +0000 Received: by mail-wm1-x344.google.com with SMTP id n25so12676090wmk.4 for ; Mon, 20 May 2019 06:38:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MZ9lTWI+Lc/C+oK4npZx3sJLpiEnZG/zd/AYB4si+t8=; b=Dkz9NX5IhZv8/njLB0RdVNKRYnHa9zrgXGtpigEfsfXpFkTycOX2nFKMU9jIygylDX btHlra31XFxIEiN7N5StNn8jsrEG3BUm/Bgf4Bz0rizMyQZtMEp5uSJUYt0vOJTd0a41 tlTX7oQu/31UR2r42+cyddgrglS9F2j6m7Tvjn8n7Hnor2w4Kp7M81HUayar6cna0ln7 aOp+qq3JQugEW8eo+W9WyjTF7XbwU3FOwAzmw0HmcagS94zixdFj15Y6cCPT+z7rJeb3 xFh11xoNyCK1qL4cr3bTgzJkGAdHcdNa3G14KbhkWkgDCo5EctlNtNsO6czXYyNxvXgZ ttLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MZ9lTWI+Lc/C+oK4npZx3sJLpiEnZG/zd/AYB4si+t8=; b=fl23PLXB0QNNR1VDSLa7cYkLDJazKo2ej2oDm/MeW0w51hhmYwueX63i/BlxtK/J9m cLxckPfw/7Wxd3uVU6v4ybPFEEadGN/dykSOlzeoJmkcLbsfpP1tjg0Nn25hnx3hK9Yd ORGaOTPlYQS3QvTqN2F0idmtUeuK5mc+OLPy2sofvsUo1HPyAfJPonW0VZS6v50EGksB Nwp/n3ozLh48EnMKfAxbCLYu1HddNnPZU20qyO+QU+EMSTkw9DpRUWT7EF3QVWBFPEwF Wja7ReNQbKcbOe1+HvO/hAqKtK1IiXgQDhPUEzWZvLGmkwDWfPS4/8xy10KngomvM03G 9iPQ== X-Gm-Message-State: APjAAAXm9/xVRn4i5I8OgZS2wPTBd63FWQaePxNTAkYI3APieCDKPrjJ ldlYLWajnxaEfHi68s6tB8OkGKLhyJswBA== X-Google-Smtp-Source: APXvYqxa5RaiIeHtqDyp7p2Aeh02OdD024JHejqByLNaNF33pGnOdgb4OUGNF/0uxiMAQY8Wau1bKg== X-Received: by 2002:a1c:cb81:: with SMTP id b123mr11978006wmg.107.1558359481053; Mon, 20 May 2019 06:38:01 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id t19sm12167059wmi.42.2019.05.20.06.37.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 May 2019 06:38:00 -0700 (PDT) From: Neil Armstrong To: a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com Subject: [PATCH 4/5] drm/meson: Add YUV420 output support Date: Mon, 20 May 2019 15:37:52 +0200 Message-Id: <20190520133753.23871-5-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190520133753.23871-1-narmstrong@baylibre.com> References: <20190520133753.23871-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_063803_144858_B30ED89C X-CRM114-Status: GOOD ( 22.39 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jernej.skrabec@siol.net, heiko@sntech.de, Neil Armstrong , maxime.ripard@bootlin.com, jonas@kwiboo.se, hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, hverkuil@xs4all.nl, linux-amlogic@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org This patch adds support for the YUV420 output from the Amlogic Meson SoCs Video Processing Unit to the HDMI Controller. The YUV420 is obtained by generating a YUV444 pixel stream like the classic HDMI display modes, but then the Video Encoder output can be configured to down-sample the YUV444 pixel stream to a YUV420 stream. In addition if pixel stream down-sampling, the Y Cb Cr components must also be mapped differently to align with the HDMI2.0 specifications. This mode needs a different clock generation scheme since the TMDS PHY clock must match the 10x ration with the YUV420 pixel clock, but the video encoder must run at 2x the pixel clock. This patch adds the TMDS PHY clock value in all the video clock setup in order to better support these specific uses cases and switch to the Common Clock framework for clocks handling in the future. When 420 is needed, it calls drm_bridge_format_set() for notify the bridge the input format has changed to YUV420. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_dw_hdmi.c | 100 +++++++++++++++++++----- drivers/gpu/drm/meson/meson_vclk.c | 93 ++++++++++++++++------ drivers/gpu/drm/meson/meson_vclk.h | 7 +- drivers/gpu/drm/meson/meson_venc.c | 6 +- drivers/gpu/drm/meson/meson_venc.h | 11 +++ drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- 6 files changed, 174 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index 779da21143b9..5d67e2beba58 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -159,6 +159,7 @@ struct meson_dw_hdmi { struct regulator *hdmi_supply; u32 irq_stat; struct dw_hdmi *hdmi; + unsigned long input_bus_format; }; #define encoder_to_meson_dw_hdmi(x) \ container_of(x, struct meson_dw_hdmi, encoder) @@ -308,6 +309,10 @@ static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi, struct meson_drm *priv = dw_hdmi->priv; unsigned int pixel_clock = mode->clock; + /* For 420, pixel clock is half unlike venc clock */ + if (dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24) + pixel_clock /= 2; + if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) { if (pixel_clock >= 371250) { @@ -383,25 +388,36 @@ static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi, { struct meson_drm *priv = dw_hdmi->priv; int vic = drm_match_cea_mode(mode); + unsigned int phy_freq; unsigned int vclk_freq; unsigned int venc_freq; unsigned int hdmi_freq; vclk_freq = mode->clock; + /* For 420, pixel clock is half unlike venc clock */ + if (dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24) + vclk_freq /= 2; + + /* TMDS clock is pixel_clock * 10 */ + phy_freq = vclk_freq * 10; + if (!vic) { - meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, vclk_freq, - vclk_freq, vclk_freq, false); + meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, phy_freq, + vclk_freq, vclk_freq, vclk_freq, false); return; } + /* 480i/576i needs global pixel doubling */ if (mode->flags & DRM_MODE_FLAG_DBLCLK) vclk_freq *= 2; venc_freq = vclk_freq; hdmi_freq = vclk_freq; - if (meson_venc_hdmi_venc_repeat(vic)) + /* VENC double pixels for 1080i, 720p and YUV420 modes */ + if (meson_venc_hdmi_venc_repeat(vic) || + dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24) venc_freq *= 2; vclk_freq = max(venc_freq, hdmi_freq); @@ -409,11 +425,11 @@ static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi, if (mode->flags & DRM_MODE_FLAG_DBLCLK) venc_freq /= 2; - DRM_DEBUG_DRIVER("vclk:%d venc=%d hdmi=%d enci=%d\n", - vclk_freq, venc_freq, hdmi_freq, + DRM_DEBUG_DRIVER("vclk:%d phy=%d venc=%d hdmi=%d enci=%d\n", + phy_freq, vclk_freq, venc_freq, hdmi_freq, priv->venc.hdmi_use_enci); - meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, vclk_freq, + meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, phy_freq, vclk_freq, venc_freq, hdmi_freq, priv->venc.hdmi_use_enci); } @@ -446,8 +462,9 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, /* Enable normal output to PHY */ dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12)); - /* TMDS pattern setup (TOFIX Handle the YUV420 case) */ - if (mode->clock > 340000) { + /* TMDS pattern setup */ + if (mode->clock > 340000 && + dw_hdmi->input_bus_format == MEDIA_BUS_FMT_YUV8_1X24) { dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0); dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, @@ -622,6 +639,8 @@ dw_hdmi_mode_valid(struct drm_connector *connector, const struct drm_display_mode *mode) { struct meson_drm *priv = connector->dev->dev_private; + bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported; + unsigned int phy_freq; unsigned int vclk_freq; unsigned int venc_freq; unsigned int hdmi_freq; @@ -630,9 +649,11 @@ dw_hdmi_mode_valid(struct drm_connector *connector, DRM_DEBUG_DRIVER("Modeline " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); - /* If sink max TMDS clock, we reject the mode */ + /* If sink does not support 540MHz, reject the non-420 HDMI2 modes */ if (connector->display_info.max_tmds_clock && - mode->clock > connector->display_info.max_tmds_clock) + mode->clock > connector->display_info.max_tmds_clock && + !drm_mode_is_420_only(&connector->display_info, mode) && + !drm_mode_is_420_also(&connector->display_info, mode)) return MODE_BAD; /* Check against non-VIC supported modes */ @@ -648,6 +669,15 @@ dw_hdmi_mode_valid(struct drm_connector *connector, vclk_freq = mode->clock; + /* For 420, pixel clock is half unlike venc clock */ + if (drm_mode_is_420_only(&connector->display_info, mode) || + (!is_hdmi2_sink && + drm_mode_is_420_also(&connector->display_info, mode))) + vclk_freq /= 2; + + /* TMDS clock is pixel_clock * 10 */ + phy_freq = vclk_freq * 10; + /* 480i/576i needs global pixel doubling */ if (mode->flags & DRM_MODE_FLAG_DBLCLK) vclk_freq *= 2; @@ -655,8 +685,11 @@ dw_hdmi_mode_valid(struct drm_connector *connector, venc_freq = vclk_freq; hdmi_freq = vclk_freq; - /* VENC double pixels for 1080i and 720p modes */ - if (meson_venc_hdmi_venc_repeat(vic)) + /* VENC double pixels for 1080i, 720p and YUV420 modes */ + if (meson_venc_hdmi_venc_repeat(vic) || + drm_mode_is_420_only(&connector->display_info, mode) || + (!is_hdmi2_sink && + drm_mode_is_420_also(&connector->display_info, mode))) venc_freq *= 2; vclk_freq = max(venc_freq, hdmi_freq); @@ -664,10 +697,10 @@ dw_hdmi_mode_valid(struct drm_connector *connector, if (mode->flags & DRM_MODE_FLAG_DBLCLK) venc_freq /= 2; - dev_dbg(connector->dev->dev, "%s: vclk:%d venc=%d hdmi=%d\n", __func__, - vclk_freq, venc_freq, hdmi_freq); + dev_dbg(connector->dev->dev, "%s: vclk:%d phy=%d venc=%d hdmi=%d\n", + __func__, phy_freq, vclk_freq, venc_freq, hdmi_freq); - return meson_vclk_vic_supported_freq(vclk_freq); + return meson_vclk_vic_supported_freq(phy_freq, vclk_freq); } /* Encoder */ @@ -685,6 +718,24 @@ static int meson_venc_hdmi_encoder_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); + struct drm_display_info *info = &conn_state->connector->display_info; + struct drm_display_mode *mode = &crtc_state->mode; + bool is_hdmi2_sink = + conn_state->connector->display_info.hdmi.scdc.supported; + + if (drm_mode_is_420_only(info, mode) || + (!is_hdmi2_sink && drm_mode_is_420_also(info, mode))) + dw_hdmi->input_bus_format = MEDIA_BUS_FMT_UYYVYY8_0_5X24; + else + dw_hdmi->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24; + + /* Specify the encoder output format to the bridge */ + if (!drm_bridge_format_set(encoder->bridge, + dw_hdmi->input_bus_format, + V4L2_YCBCR_ENC_709)) + return -EINVAL; + return 0; } @@ -722,17 +773,29 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder *encoder, struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); struct meson_drm *priv = dw_hdmi->priv; int vic = drm_match_cea_mode(mode); + unsigned int ycrcb_map = MESON_VENC_MAP_CB_Y_CR; + bool yuv420_mode = false; DRM_DEBUG_DRIVER("\"%s\" vic %d\n", mode->name, vic); + if (dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24) { + ycrcb_map = MESON_VENC_MAP_CR_Y_CB; + yuv420_mode = true; + } + /* VENC + VENC-DVI Mode setup */ - meson_venc_hdmi_mode_set(priv, vic, mode); + meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, yuv420_mode, mode); /* VCLK Set clock */ dw_hdmi_set_vclk(dw_hdmi, mode); - /* Setup YUV444 to HDMI-TX, no 10bit diphering */ - writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); + if (dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24) + /* Setup YUV420 to HDMI-TX, no 10bit diphering */ + writel_relaxed(2 | (2 << 2), + priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); + else + /* Setup YUV444 to HDMI-TX, no 10bit diphering */ + writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); } static const struct drm_encoder_helper_funcs @@ -977,6 +1040,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master, dw_plat_data->phy_data = meson_dw_hdmi; dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24; dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709; + dw_plat_data->ycbcr_420_allowed = true; platform_set_drvdata(pdev, meson_dw_hdmi); diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c index b39034745444..44250eff8a3f 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -364,12 +364,17 @@ enum { /* 2970 /1 /1 /1 /5 /2 => /1 /1 */ MESON_VCLK_HDMI_297000, /* 5940 /1 /1 /2 /5 /1 => /1 /1 */ - MESON_VCLK_HDMI_594000 + MESON_VCLK_HDMI_594000, +/* 2970 /1 /1 /1 /5 /1 => /1 /2 */ + MESON_VCLK_HDMI_594000_YUV420, }; struct meson_vclk_params { + unsigned int pll_freq; + unsigned int phy_freq; + unsigned int vclk_freq; + unsigned int venc_freq; unsigned int pixel_freq; - unsigned int pll_base_freq; unsigned int pll_od1; unsigned int pll_od2; unsigned int pll_od3; @@ -377,8 +382,11 @@ struct meson_vclk_params { unsigned int vclk_div; } params[] = { [MESON_VCLK_HDMI_ENCI_54000] = { + .pll_freq = 4320000, + .phy_freq = 270000, + .vclk_freq = 54000, + .venc_freq = 54000, .pixel_freq = 54000, - .pll_base_freq = 4320000, .pll_od1 = 4, .pll_od2 = 4, .pll_od3 = 1, @@ -386,8 +394,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_DDR_54000] = { - .pixel_freq = 54000, - .pll_base_freq = 4320000, + .pll_freq = 4320000, + .phy_freq = 270000, + .vclk_freq = 54000, + .venc_freq = 54000, + .pixel_freq = 27000, .pll_od1 = 4, .pll_od2 = 4, .pll_od3 = 1, @@ -395,8 +406,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_DDR_148500] = { - .pixel_freq = 148500, - .pll_base_freq = 2970000, + .pll_freq = 2970000, + .phy_freq = 742500, + .vclk_freq = 148500, + .venc_freq = 148500, + .pixel_freq = 74250, .pll_od1 = 4, .pll_od2 = 1, .pll_od3 = 1, @@ -404,8 +418,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_74250] = { + .pll_freq = 2970000, + .phy_freq = 742500, + .vclk_freq = 74250, + .venc_freq = 74250, .pixel_freq = 74250, - .pll_base_freq = 2970000, .pll_od1 = 2, .pll_od2 = 2, .pll_od3 = 2, @@ -413,8 +430,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_148500] = { + .pll_freq = 2970000, + .phy_freq = 1485000, + .vclk_freq = 148500, + .venc_freq = 148500, .pixel_freq = 148500, - .pll_base_freq = 2970000, .pll_od1 = 1, .pll_od2 = 2, .pll_od3 = 2, @@ -422,8 +442,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_297000] = { + .pll_freq = 5940000, + .phy_freq = 2970000, + .venc_freq = 297000, + .vclk_freq = 297000, .pixel_freq = 297000, - .pll_base_freq = 5940000, .pll_od1 = 2, .pll_od2 = 1, .pll_od3 = 1, @@ -431,14 +454,29 @@ struct meson_vclk_params { .vclk_div = 2, }, [MESON_VCLK_HDMI_594000] = { + .pll_freq = 5940000, + .phy_freq = 5940000, + .venc_freq = 594000, + .vclk_freq = 594000, .pixel_freq = 594000, - .pll_base_freq = 5940000, .pll_od1 = 1, .pll_od2 = 1, .pll_od3 = 2, .vid_pll_div = VID_PLL_DIV_5, .vclk_div = 1, }, + [MESON_VCLK_HDMI_594000_YUV420] = { + .pll_freq = 5940000, + .phy_freq = 2970000, + .venc_freq = 594000, + .vclk_freq = 594000, + .pixel_freq = 297000, + .pll_od1 = 2, + .pll_od2 = 1, + .pll_od3 = 1, + .vid_pll_div = VID_PLL_DIV_5, + .vclk_div = 1, + }, { /* sentinel */ }, }; @@ -696,6 +734,7 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv, unsigned int od, m, frac, od1, od2, od3; if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) { + /* OD2 goes to the PHY, and needs to be *10, so keep OD3=1 */ od3 = 1; if (od < 4) { od1 = 2; @@ -718,21 +757,28 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv, } enum drm_mode_status -meson_vclk_vic_supported_freq(unsigned int freq) +meson_vclk_vic_supported_freq(unsigned int phy_freq, + unsigned int vclk_freq) { int i; - DRM_DEBUG_DRIVER("freq = %d\n", freq); + DRM_DEBUG_DRIVER("phy_freq = %d vclk_freq = %d\n", + phy_freq, vclk_freq); for (i = 0 ; params[i].pixel_freq ; ++i) { DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n", i, params[i].pixel_freq, FREQ_1000_1001(params[i].pixel_freq)); + DRM_DEBUG_DRIVER("i = %d phy_freq = %d alt = %d\n", + i, params[i].phy_freq, + FREQ_1000_1001(params[i].phy_freq/10)*10); /* Match strict frequency */ - if (freq == params[i].pixel_freq) + if (phy_freq == params[i].phy_freq && + vclk_freq == params[i].vclk_freq) return MODE_OK; /* Match 1000/1001 variant */ - if (freq == FREQ_1000_1001(params[i].pixel_freq)) + if (phy_freq == (FREQ_1000_1001(params[i].phy_freq/10)*10) && + vclk_freq == FREQ_1000_1001(params[i].vclk_freq)) return MODE_OK; } @@ -960,8 +1006,9 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq, } void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int vclk_freq, unsigned int venc_freq, - unsigned int dac_freq, bool hdmi_use_enci) + unsigned int phy_freq, unsigned int vclk_freq, + unsigned int venc_freq, unsigned int dac_freq, + bool hdmi_use_enci) { bool vic_alternate_clock = false; unsigned int freq; @@ -980,7 +1027,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, * - venc_div = 1 * - encp encoder */ - meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0, + meson_vclk_set(priv, phy_freq, 0, 0, 0, VID_PLL_DIV_5, 2, 1, 1, false, false); return; } @@ -1002,9 +1049,11 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, } for (freq = 0 ; params[freq].pixel_freq ; ++freq) { - if (vclk_freq == params[freq].pixel_freq || - vclk_freq == FREQ_1000_1001(params[freq].pixel_freq)) { - if (vclk_freq != params[freq].pixel_freq) + if ((phy_freq == params[freq].phy_freq || + phy_freq == FREQ_1000_1001(params[freq].phy_freq/10)*10) && + (vclk_freq == params[freq].vclk_freq || + vclk_freq == FREQ_1000_1001(params[freq].vclk_freq))) { + if (vclk_freq != params[freq].vclk_freq) vic_alternate_clock = true; else vic_alternate_clock = false; @@ -1033,7 +1082,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, return; } - meson_vclk_set(priv, params[freq].pll_base_freq, + meson_vclk_set(priv, params[freq].pll_freq, params[freq].pll_od1, params[freq].pll_od2, params[freq].pll_od3, params[freq].vid_pll_div, params[freq].vclk_div, hdmi_tx_div, venc_div, diff --git a/drivers/gpu/drm/meson/meson_vclk.h b/drivers/gpu/drm/meson/meson_vclk.h index 4bd8752da02a..c4d19ddfcd79 100644 --- a/drivers/gpu/drm/meson/meson_vclk.h +++ b/drivers/gpu/drm/meson/meson_vclk.h @@ -33,10 +33,11 @@ enum { enum drm_mode_status meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq); enum drm_mode_status -meson_vclk_vic_supported_freq(unsigned int freq); +meson_vclk_vic_supported_freq(unsigned int phy_freq, unsigned int vclk_freq); void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int vclk_freq, unsigned int venc_freq, - unsigned int dac_freq, bool hdmi_use_enci); + unsigned int phy_freq, unsigned int vclk_freq, + unsigned int venc_freq, unsigned int dac_freq, + bool hdmi_use_enci); #endif /* __MESON_VCLK_H */ diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c index 6faca7313339..5460c4439612 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -958,6 +958,8 @@ bool meson_venc_hdmi_venc_repeat(int vic) EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat); void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, + unsigned int ycrcb_map, + bool yuv420_mode, struct drm_display_mode *mode) { union meson_hdmi_venc_mode *vmode = NULL; @@ -1508,8 +1510,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, writel_relaxed((use_enci ? 1 : 2) | (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) | (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) | - 4 << 5 | - (venc_repeat ? 1 << 8 : 0) | + (ycrcb_map << 5) | + (venc_repeat || yuv420_mode ? 1 << 8 : 0) | (hdmi_repeat ? 1 << 12 : 0), priv->io_base + _REG(VPU_HDMI_SETTING)); diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h index 97eaebbfa0c4..5580bf38e381 100644 --- a/drivers/gpu/drm/meson/meson_venc.h +++ b/drivers/gpu/drm/meson/meson_venc.h @@ -33,6 +33,15 @@ enum { MESON_VENC_MODE_HDMI, }; +enum { + MESON_VENC_MAP_CR_Y_CB = 0, + MESON_VENC_MAP_Y_CB_CR, + MESON_VENC_MAP_Y_CR_CB, + MESON_VENC_MAP_CB_CR_Y, + MESON_VENC_MAP_CB_Y_CR, + MESON_VENC_MAP_CR_CB_Y, +}; + struct meson_cvbs_enci_mode { unsigned int mode_tag; unsigned int hso_begin; /* HSO begin position */ @@ -70,6 +79,8 @@ extern struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc; void meson_venci_cvbs_mode_set(struct meson_drm *priv, struct meson_cvbs_enci_mode *mode); void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, + unsigned int ycrcb_map, + bool yuv420_mode, struct drm_display_mode *mode); unsigned int meson_venci_get_field(struct meson_drm *priv); diff --git a/drivers/gpu/drm/meson/meson_venc_cvbs.c b/drivers/gpu/drm/meson/meson_venc_cvbs.c index 2c5341c881c4..c1bbc601cf13 100644 --- a/drivers/gpu/drm/meson/meson_venc_cvbs.c +++ b/drivers/gpu/drm/meson/meson_venc_cvbs.c @@ -218,7 +218,8 @@ static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder, /* Setup 27MHz vclk2 for ENCI and VDAC */ meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS, MESON_VCLK_CVBS, MESON_VCLK_CVBS, - MESON_VCLK_CVBS, true); + MESON_VCLK_CVBS, MESON_VCLK_CVBS, + true); break; } } -- 2.21.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic From mboxrd@z Thu Jan 1 00:00:00 1970 From: Neil Armstrong Subject: [PATCH 4/5] drm/meson: Add YUV420 output support Date: Mon, 20 May 2019 15:37:52 +0200 Message-ID: <20190520133753.23871-5-narmstrong@baylibre.com> References: <20190520133753.23871-1-narmstrong@baylibre.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1607A8929D for ; Mon, 20 May 2019 13:38:04 +0000 (UTC) Received: by mail-wm1-x343.google.com with SMTP id t5so11732112wmh.3 for ; Mon, 20 May 2019 06:38:04 -0700 (PDT) In-Reply-To: <20190520133753.23871-1-narmstrong@baylibre.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com Cc: jernej.skrabec@siol.net, Neil Armstrong , maxime.ripard@bootlin.com, jonas@kwiboo.se, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, hverkuil@xs4all.nl, linux-amlogic@lists.infradead.org List-Id: dri-devel@lists.freedesktop.org VGhpcyBwYXRjaCBhZGRzIHN1cHBvcnQgZm9yIHRoZSBZVVY0MjAgb3V0cHV0IGZyb20gdGhlIEFt bG9naWMgTWVzb24gU29DcwpWaWRlbyBQcm9jZXNzaW5nIFVuaXQgdG8gdGhlIEhETUkgQ29udHJv bGxlci4KClRoZSBZVVY0MjAgaXMgb2J0YWluZWQgYnkgZ2VuZXJhdGluZyBhIFlVVjQ0NCBwaXhl bCBzdHJlYW0gbGlrZQp0aGUgY2xhc3NpYyBIRE1JIGRpc3BsYXkgbW9kZXMsIGJ1dCB0aGVuIHRo ZSBWaWRlbyBFbmNvZGVyIG91dHB1dApjYW4gYmUgY29uZmlndXJlZCB0byBkb3duLXNhbXBsZSB0 aGUgWVVWNDQ0IHBpeGVsIHN0cmVhbSB0byBhIFlVVjQyMApzdHJlYW0uCkluIGFkZGl0aW9uIGlm IHBpeGVsIHN0cmVhbSBkb3duLXNhbXBsaW5nLCB0aGUgWSBDYiBDciBjb21wb25lbnRzIG11c3QK YWxzbyBiZSBtYXBwZWQgZGlmZmVyZW50bHkgdG8gYWxpZ24gd2l0aCB0aGUgSERNSTIuMCBzcGVj aWZpY2F0aW9ucy4KClRoaXMgbW9kZSBuZWVkcyBhIGRpZmZlcmVudCBjbG9jayBnZW5lcmF0aW9u IHNjaGVtZSBzaW5jZSB0aGUgVE1EUyBQSFkKY2xvY2sgbXVzdCBtYXRjaCB0aGUgMTB4IHJhdGlv biB3aXRoIHRoZSBZVVY0MjAgcGl4ZWwgY2xvY2ssIGJ1dAp0aGUgdmlkZW8gZW5jb2RlciBtdXN0 IHJ1biBhdCAyeCB0aGUgcGl4ZWwgY2xvY2suCgpUaGlzIHBhdGNoIGFkZHMgdGhlIFRNRFMgUEhZ IGNsb2NrIHZhbHVlIGluIGFsbCB0aGUgdmlkZW8gY2xvY2sgc2V0dXAKaW4gb3JkZXIgdG8gYmV0 dGVyIHN1cHBvcnQgdGhlc2Ugc3BlY2lmaWMgdXNlcyBjYXNlcyBhbmQgc3dpdGNoCnRvIHRoZSBD b21tb24gQ2xvY2sgZnJhbWV3b3JrIGZvciBjbG9ja3MgaGFuZGxpbmcgaW4gdGhlIGZ1dHVyZS4K CldoZW4gNDIwIGlzIG5lZWRlZCwgaXQgY2FsbHMgZHJtX2JyaWRnZV9mb3JtYXRfc2V0KCkgZm9y IG5vdGlmeSB0aGUKYnJpZGdlIHRoZSBpbnB1dCBmb3JtYXQgaGFzIGNoYW5nZWQgdG8gWVVWNDIw LgoKU2lnbmVkLW9mZi1ieTogTmVpbCBBcm1zdHJvbmcgPG5hcm1zdHJvbmdAYmF5bGlicmUuY29t PgotLS0KIGRyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNvbl9kd19oZG1pLmMgICB8IDEwMCArKysr KysrKysrKysrKysrKysrLS0tLS0KIGRyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNvbl92Y2xrLmMg ICAgICB8ICA5MyArKysrKysrKysrKysrKysrLS0tLS0tCiBkcml2ZXJzL2dwdS9kcm0vbWVzb24v bWVzb25fdmNsay5oICAgICAgfCAgIDcgKy0KIGRyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNvbl92 ZW5jLmMgICAgICB8ICAgNiArLQogZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX3ZlbmMuaCAg ICAgIHwgIDExICsrKwogZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX3ZlbmNfY3Zicy5jIHwg ICAzICstCiA2IGZpbGVzIGNoYW5nZWQsIDE3NCBpbnNlcnRpb25zKCspLCA0NiBkZWxldGlvbnMo LSkKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25fZHdfaGRtaS5jIGIv ZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX2R3X2hkbWkuYwppbmRleCA3NzlkYTIxMTQzYjku LjVkNjdlMmJlYmE1OCAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX2R3 X2hkbWkuYworKysgYi9kcml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25fZHdfaGRtaS5jCkBAIC0x NTksNiArMTU5LDcgQEAgc3RydWN0IG1lc29uX2R3X2hkbWkgewogCXN0cnVjdCByZWd1bGF0b3Ig KmhkbWlfc3VwcGx5OwogCXUzMiBpcnFfc3RhdDsKIAlzdHJ1Y3QgZHdfaGRtaSAqaGRtaTsKKwl1 bnNpZ25lZCBsb25nIGlucHV0X2J1c19mb3JtYXQ7CiB9OwogI2RlZmluZSBlbmNvZGVyX3RvX21l c29uX2R3X2hkbWkoeCkgXAogCWNvbnRhaW5lcl9vZih4LCBzdHJ1Y3QgbWVzb25fZHdfaGRtaSwg ZW5jb2RlcikKQEAgLTMwOCw2ICszMDksMTAgQEAgc3RhdGljIHZvaWQgbWVzb25faGRtaV9waHlf c2V0dXBfbW9kZShzdHJ1Y3QgbWVzb25fZHdfaGRtaSAqZHdfaGRtaSwKIAlzdHJ1Y3QgbWVzb25f ZHJtICpwcml2ID0gZHdfaGRtaS0+cHJpdjsKIAl1bnNpZ25lZCBpbnQgcGl4ZWxfY2xvY2sgPSBt b2RlLT5jbG9jazsKIAorCS8qIEZvciA0MjAsIHBpeGVsIGNsb2NrIGlzIGhhbGYgdW5saWtlIHZl bmMgY2xvY2sgKi8KKwlpZiAoZHdfaGRtaS0+aW5wdXRfYnVzX2Zvcm1hdCA9PSBNRURJQV9CVVNf Rk1UX1VZWVZZWThfMF81WDI0KQorCQlwaXhlbF9jbG9jayAvPSAyOworCiAJaWYgKGR3X2hkbWlf aXNfY29tcGF0aWJsZShkd19oZG1pLCAiYW1sb2dpYyxtZXNvbi1neGwtZHctaGRtaSIpIHx8CiAJ ICAgIGR3X2hkbWlfaXNfY29tcGF0aWJsZShkd19oZG1pLCAiYW1sb2dpYyxtZXNvbi1neG0tZHct aGRtaSIpKSB7CiAJCWlmIChwaXhlbF9jbG9jayA+PSAzNzEyNTApIHsKQEAgLTM4MywyNSArMzg4 LDM2IEBAIHN0YXRpYyB2b2lkIGR3X2hkbWlfc2V0X3ZjbGsoc3RydWN0IG1lc29uX2R3X2hkbWkg KmR3X2hkbWksCiB7CiAJc3RydWN0IG1lc29uX2RybSAqcHJpdiA9IGR3X2hkbWktPnByaXY7CiAJ aW50IHZpYyA9IGRybV9tYXRjaF9jZWFfbW9kZShtb2RlKTsKKwl1bnNpZ25lZCBpbnQgcGh5X2Zy ZXE7CiAJdW5zaWduZWQgaW50IHZjbGtfZnJlcTsKIAl1bnNpZ25lZCBpbnQgdmVuY19mcmVxOwog CXVuc2lnbmVkIGludCBoZG1pX2ZyZXE7CiAKIAl2Y2xrX2ZyZXEgPSBtb2RlLT5jbG9jazsKIAor CS8qIEZvciA0MjAsIHBpeGVsIGNsb2NrIGlzIGhhbGYgdW5saWtlIHZlbmMgY2xvY2sgKi8KKwlp ZiAoZHdfaGRtaS0+aW5wdXRfYnVzX2Zvcm1hdCA9PSBNRURJQV9CVVNfRk1UX1VZWVZZWThfMF81 WDI0KQorCQl2Y2xrX2ZyZXEgLz0gMjsKKworCS8qIFRNRFMgY2xvY2sgaXMgcGl4ZWxfY2xvY2sg KiAxMCAqLworCXBoeV9mcmVxID0gdmNsa19mcmVxICogMTA7CisKIAlpZiAoIXZpYykgewotCQlt ZXNvbl92Y2xrX3NldHVwKHByaXYsIE1FU09OX1ZDTEtfVEFSR0VUX0RNVCwgdmNsa19mcmVxLAot CQkJCSB2Y2xrX2ZyZXEsIHZjbGtfZnJlcSwgZmFsc2UpOworCQltZXNvbl92Y2xrX3NldHVwKHBy aXYsIE1FU09OX1ZDTEtfVEFSR0VUX0RNVCwgcGh5X2ZyZXEsCisJCQkJIHZjbGtfZnJlcSwgdmNs a19mcmVxLCB2Y2xrX2ZyZXEsIGZhbHNlKTsKIAkJcmV0dXJuOwogCX0KIAorCS8qIDQ4MGkvNTc2 aSBuZWVkcyBnbG9iYWwgcGl4ZWwgZG91YmxpbmcgKi8KIAlpZiAobW9kZS0+ZmxhZ3MgJiBEUk1f TU9ERV9GTEFHX0RCTENMSykKIAkJdmNsa19mcmVxICo9IDI7CiAKIAl2ZW5jX2ZyZXEgPSB2Y2xr X2ZyZXE7CiAJaGRtaV9mcmVxID0gdmNsa19mcmVxOwogCi0JaWYgKG1lc29uX3ZlbmNfaGRtaV92 ZW5jX3JlcGVhdCh2aWMpKQorCS8qIFZFTkMgZG91YmxlIHBpeGVscyBmb3IgMTA4MGksIDcyMHAg YW5kIFlVVjQyMCBtb2RlcyAqLworCWlmIChtZXNvbl92ZW5jX2hkbWlfdmVuY19yZXBlYXQodmlj KSB8fAorCSAgICBkd19oZG1pLT5pbnB1dF9idXNfZm9ybWF0ID09IE1FRElBX0JVU19GTVRfVVlZ VllZOF8wXzVYMjQpCiAJCXZlbmNfZnJlcSAqPSAyOwogCiAJdmNsa19mcmVxID0gbWF4KHZlbmNf ZnJlcSwgaGRtaV9mcmVxKTsKQEAgLTQwOSwxMSArNDI1LDExIEBAIHN0YXRpYyB2b2lkIGR3X2hk bWlfc2V0X3ZjbGsoc3RydWN0IG1lc29uX2R3X2hkbWkgKmR3X2hkbWksCiAJaWYgKG1vZGUtPmZs YWdzICYgRFJNX01PREVfRkxBR19EQkxDTEspCiAJCXZlbmNfZnJlcSAvPSAyOwogCi0JRFJNX0RF QlVHX0RSSVZFUigidmNsazolZCB2ZW5jPSVkIGhkbWk9JWQgZW5jaT0lZFxuIiwKLQkJdmNsa19m cmVxLCB2ZW5jX2ZyZXEsIGhkbWlfZnJlcSwKKwlEUk1fREVCVUdfRFJJVkVSKCJ2Y2xrOiVkIHBo eT0lZCB2ZW5jPSVkIGhkbWk9JWQgZW5jaT0lZFxuIiwKKwkJcGh5X2ZyZXEsIHZjbGtfZnJlcSwg dmVuY19mcmVxLCBoZG1pX2ZyZXEsCiAJCXByaXYtPnZlbmMuaGRtaV91c2VfZW5jaSk7CiAKLQlt ZXNvbl92Y2xrX3NldHVwKHByaXYsIE1FU09OX1ZDTEtfVEFSR0VUX0hETUksIHZjbGtfZnJlcSwK KwltZXNvbl92Y2xrX3NldHVwKHByaXYsIE1FU09OX1ZDTEtfVEFSR0VUX0hETUksIHBoeV9mcmVx LCB2Y2xrX2ZyZXEsCiAJCQkgdmVuY19mcmVxLCBoZG1pX2ZyZXEsIHByaXYtPnZlbmMuaGRtaV91 c2VfZW5jaSk7CiB9CiAKQEAgLTQ0Niw4ICs0NjIsOSBAQCBzdGF0aWMgaW50IGR3X2hkbWlfcGh5 X2luaXQoc3RydWN0IGR3X2hkbWkgKmhkbWksIHZvaWQgKmRhdGEsCiAJLyogRW5hYmxlIG5vcm1h bCBvdXRwdXQgdG8gUEhZICovCiAJZHdfaGRtaS0+ZGF0YS0+dG9wX3dyaXRlKGR3X2hkbWksIEhE TUlUWF9UT1BfQklTVF9DTlRMLCBCSVQoMTIpKTsKIAotCS8qIFRNRFMgcGF0dGVybiBzZXR1cCAo VE9GSVggSGFuZGxlIHRoZSBZVVY0MjAgY2FzZSkgKi8KLQlpZiAobW9kZS0+Y2xvY2sgPiAzNDAw MDApIHsKKwkvKiBUTURTIHBhdHRlcm4gc2V0dXAgKi8KKwlpZiAobW9kZS0+Y2xvY2sgPiAzNDAw MDAgJiYKKwkgICAgZHdfaGRtaS0+aW5wdXRfYnVzX2Zvcm1hdCA9PSBNRURJQV9CVVNfRk1UX1lV VjhfMVgyNCkgewogCQlkd19oZG1pLT5kYXRhLT50b3Bfd3JpdGUoZHdfaGRtaSwgSERNSVRYX1RP UF9UTURTX0NMS19QVFROXzAxLAogCQkJCSAgMCk7CiAJCWR3X2hkbWktPmRhdGEtPnRvcF93cml0 ZShkd19oZG1pLCBIRE1JVFhfVE9QX1RNRFNfQ0xLX1BUVE5fMjMsCkBAIC02MjIsNiArNjM5LDgg QEAgZHdfaGRtaV9tb2RlX3ZhbGlkKHN0cnVjdCBkcm1fY29ubmVjdG9yICpjb25uZWN0b3IsCiAJ CSAgIGNvbnN0IHN0cnVjdCBkcm1fZGlzcGxheV9tb2RlICptb2RlKQogewogCXN0cnVjdCBtZXNv bl9kcm0gKnByaXYgPSBjb25uZWN0b3ItPmRldi0+ZGV2X3ByaXZhdGU7CisJYm9vbCBpc19oZG1p Ml9zaW5rID0gY29ubmVjdG9yLT5kaXNwbGF5X2luZm8uaGRtaS5zY2RjLnN1cHBvcnRlZDsKKwl1 bnNpZ25lZCBpbnQgcGh5X2ZyZXE7CiAJdW5zaWduZWQgaW50IHZjbGtfZnJlcTsKIAl1bnNpZ25l ZCBpbnQgdmVuY19mcmVxOwogCXVuc2lnbmVkIGludCBoZG1pX2ZyZXE7CkBAIC02MzAsOSArNjQ5 LDExIEBAIGR3X2hkbWlfbW9kZV92YWxpZChzdHJ1Y3QgZHJtX2Nvbm5lY3RvciAqY29ubmVjdG9y LAogCiAJRFJNX0RFQlVHX0RSSVZFUigiTW9kZWxpbmUgIiBEUk1fTU9ERV9GTVQgIlxuIiwgRFJN X01PREVfQVJHKG1vZGUpKTsKIAotCS8qIElmIHNpbmsgbWF4IFRNRFMgY2xvY2ssIHdlIHJlamVj dCB0aGUgbW9kZSAqLworCS8qIElmIHNpbmsgZG9lcyBub3Qgc3VwcG9ydCA1NDBNSHosIHJlamVj dCB0aGUgbm9uLTQyMCBIRE1JMiBtb2RlcyAqLwogCWlmIChjb25uZWN0b3ItPmRpc3BsYXlfaW5m by5tYXhfdG1kc19jbG9jayAmJgotCSAgICBtb2RlLT5jbG9jayA+IGNvbm5lY3Rvci0+ZGlzcGxh eV9pbmZvLm1heF90bWRzX2Nsb2NrKQorCSAgICBtb2RlLT5jbG9jayA+IGNvbm5lY3Rvci0+ZGlz cGxheV9pbmZvLm1heF90bWRzX2Nsb2NrICYmCisJICAgICFkcm1fbW9kZV9pc180MjBfb25seSgm Y29ubmVjdG9yLT5kaXNwbGF5X2luZm8sIG1vZGUpICYmCisJICAgICFkcm1fbW9kZV9pc180MjBf YWxzbygmY29ubmVjdG9yLT5kaXNwbGF5X2luZm8sIG1vZGUpKQogCQlyZXR1cm4gTU9ERV9CQUQ7 CiAKIAkvKiBDaGVjayBhZ2FpbnN0IG5vbi1WSUMgc3VwcG9ydGVkIG1vZGVzICovCkBAIC02NDgs NiArNjY5LDE1IEBAIGR3X2hkbWlfbW9kZV92YWxpZChzdHJ1Y3QgZHJtX2Nvbm5lY3RvciAqY29u bmVjdG9yLAogCiAJdmNsa19mcmVxID0gbW9kZS0+Y2xvY2s7CiAKKwkvKiBGb3IgNDIwLCBwaXhl bCBjbG9jayBpcyBoYWxmIHVubGlrZSB2ZW5jIGNsb2NrICovCisJaWYgKGRybV9tb2RlX2lzXzQy MF9vbmx5KCZjb25uZWN0b3ItPmRpc3BsYXlfaW5mbywgbW9kZSkgfHwKKwkgICAgKCFpc19oZG1p Ml9zaW5rICYmCisJICAgICBkcm1fbW9kZV9pc180MjBfYWxzbygmY29ubmVjdG9yLT5kaXNwbGF5 X2luZm8sIG1vZGUpKSkKKwkJdmNsa19mcmVxIC89IDI7CisKKwkvKiBUTURTIGNsb2NrIGlzIHBp eGVsX2Nsb2NrICogMTAgKi8KKwlwaHlfZnJlcSA9IHZjbGtfZnJlcSAqIDEwOworCiAJLyogNDgw aS81NzZpIG5lZWRzIGdsb2JhbCBwaXhlbCBkb3VibGluZyAqLwogCWlmIChtb2RlLT5mbGFncyAm IERSTV9NT0RFX0ZMQUdfREJMQ0xLKQogCQl2Y2xrX2ZyZXEgKj0gMjsKQEAgLTY1NSw4ICs2ODUs MTEgQEAgZHdfaGRtaV9tb2RlX3ZhbGlkKHN0cnVjdCBkcm1fY29ubmVjdG9yICpjb25uZWN0b3Is CiAJdmVuY19mcmVxID0gdmNsa19mcmVxOwogCWhkbWlfZnJlcSA9IHZjbGtfZnJlcTsKIAotCS8q IFZFTkMgZG91YmxlIHBpeGVscyBmb3IgMTA4MGkgYW5kIDcyMHAgbW9kZXMgKi8KLQlpZiAobWVz b25fdmVuY19oZG1pX3ZlbmNfcmVwZWF0KHZpYykpCisJLyogVkVOQyBkb3VibGUgcGl4ZWxzIGZv ciAxMDgwaSwgNzIwcCBhbmQgWVVWNDIwIG1vZGVzICovCisJaWYgKG1lc29uX3ZlbmNfaGRtaV92 ZW5jX3JlcGVhdCh2aWMpIHx8CisJICAgIGRybV9tb2RlX2lzXzQyMF9vbmx5KCZjb25uZWN0b3It PmRpc3BsYXlfaW5mbywgbW9kZSkgfHwKKwkgICAgKCFpc19oZG1pMl9zaW5rICYmCisJICAgICBk cm1fbW9kZV9pc180MjBfYWxzbygmY29ubmVjdG9yLT5kaXNwbGF5X2luZm8sIG1vZGUpKSkKIAkJ dmVuY19mcmVxICo9IDI7CiAKIAl2Y2xrX2ZyZXEgPSBtYXgodmVuY19mcmVxLCBoZG1pX2ZyZXEp OwpAQCAtNjY0LDEwICs2OTcsMTAgQEAgZHdfaGRtaV9tb2RlX3ZhbGlkKHN0cnVjdCBkcm1fY29u bmVjdG9yICpjb25uZWN0b3IsCiAJaWYgKG1vZGUtPmZsYWdzICYgRFJNX01PREVfRkxBR19EQkxD TEspCiAJCXZlbmNfZnJlcSAvPSAyOwogCi0JZGV2X2RiZyhjb25uZWN0b3ItPmRldi0+ZGV2LCAi JXM6IHZjbGs6JWQgdmVuYz0lZCBoZG1pPSVkXG4iLCBfX2Z1bmNfXywKLQkJdmNsa19mcmVxLCB2 ZW5jX2ZyZXEsIGhkbWlfZnJlcSk7CisJZGV2X2RiZyhjb25uZWN0b3ItPmRldi0+ZGV2LCAiJXM6 IHZjbGs6JWQgcGh5PSVkIHZlbmM9JWQgaGRtaT0lZFxuIiwKKwkJX19mdW5jX18sIHBoeV9mcmVx LCB2Y2xrX2ZyZXEsIHZlbmNfZnJlcSwgaGRtaV9mcmVxKTsKIAotCXJldHVybiBtZXNvbl92Y2xr X3ZpY19zdXBwb3J0ZWRfZnJlcSh2Y2xrX2ZyZXEpOworCXJldHVybiBtZXNvbl92Y2xrX3ZpY19z dXBwb3J0ZWRfZnJlcShwaHlfZnJlcSwgdmNsa19mcmVxKTsKIH0KIAogLyogRW5jb2RlciAqLwpA QCAtNjg1LDYgKzcxOCwyNCBAQCBzdGF0aWMgaW50IG1lc29uX3ZlbmNfaGRtaV9lbmNvZGVyX2F0 b21pY19jaGVjayhzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXIsCiAJCQkJCXN0cnVjdCBkcm1f Y3J0Y19zdGF0ZSAqY3J0Y19zdGF0ZSwKIAkJCQkJc3RydWN0IGRybV9jb25uZWN0b3Jfc3RhdGUg KmNvbm5fc3RhdGUpCiB7CisJc3RydWN0IG1lc29uX2R3X2hkbWkgKmR3X2hkbWkgPSBlbmNvZGVy X3RvX21lc29uX2R3X2hkbWkoZW5jb2Rlcik7CisJc3RydWN0IGRybV9kaXNwbGF5X2luZm8gKmlu Zm8gPSAmY29ubl9zdGF0ZS0+Y29ubmVjdG9yLT5kaXNwbGF5X2luZm87CisJc3RydWN0IGRybV9k aXNwbGF5X21vZGUgKm1vZGUgPSAmY3J0Y19zdGF0ZS0+bW9kZTsKKwlib29sIGlzX2hkbWkyX3Np bmsgPQorCQljb25uX3N0YXRlLT5jb25uZWN0b3ItPmRpc3BsYXlfaW5mby5oZG1pLnNjZGMuc3Vw cG9ydGVkOworCisJaWYgKGRybV9tb2RlX2lzXzQyMF9vbmx5KGluZm8sIG1vZGUpIHx8CisJICAg ICghaXNfaGRtaTJfc2luayAmJiBkcm1fbW9kZV9pc180MjBfYWxzbyhpbmZvLCBtb2RlKSkpCisJ CWR3X2hkbWktPmlucHV0X2J1c19mb3JtYXQgPSBNRURJQV9CVVNfRk1UX1VZWVZZWThfMF81WDI0 OworCWVsc2UKKwkJZHdfaGRtaS0+aW5wdXRfYnVzX2Zvcm1hdCA9IE1FRElBX0JVU19GTVRfWVVW OF8xWDI0OworCisJLyogU3BlY2lmeSB0aGUgZW5jb2RlciBvdXRwdXQgZm9ybWF0IHRvIHRoZSBi cmlkZ2UgKi8KKwlpZiAoIWRybV9icmlkZ2VfZm9ybWF0X3NldChlbmNvZGVyLT5icmlkZ2UsCisJ CQkJICAgZHdfaGRtaS0+aW5wdXRfYnVzX2Zvcm1hdCwKKwkJCQkgICBWNEwyX1lDQkNSX0VOQ183 MDkpKQorCQlyZXR1cm4gLUVJTlZBTDsKKwogCXJldHVybiAwOwogfQogCkBAIC03MjIsMTcgKzc3 MywyOSBAQCBzdGF0aWMgdm9pZCBtZXNvbl92ZW5jX2hkbWlfZW5jb2Rlcl9tb2RlX3NldChzdHJ1 Y3QgZHJtX2VuY29kZXIgKmVuY29kZXIsCiAJc3RydWN0IG1lc29uX2R3X2hkbWkgKmR3X2hkbWkg PSBlbmNvZGVyX3RvX21lc29uX2R3X2hkbWkoZW5jb2Rlcik7CiAJc3RydWN0IG1lc29uX2RybSAq cHJpdiA9IGR3X2hkbWktPnByaXY7CiAJaW50IHZpYyA9IGRybV9tYXRjaF9jZWFfbW9kZShtb2Rl KTsKKwl1bnNpZ25lZCBpbnQgeWNyY2JfbWFwID0gTUVTT05fVkVOQ19NQVBfQ0JfWV9DUjsKKwli b29sIHl1djQyMF9tb2RlID0gZmFsc2U7CiAKIAlEUk1fREVCVUdfRFJJVkVSKCJcIiVzXCIgdmlj ICVkXG4iLCBtb2RlLT5uYW1lLCB2aWMpOwogCisJaWYgKGR3X2hkbWktPmlucHV0X2J1c19mb3Jt YXQgPT0gTUVESUFfQlVTX0ZNVF9VWVlWWVk4XzBfNVgyNCkgeworCQl5Y3JjYl9tYXAgPSBNRVNP Tl9WRU5DX01BUF9DUl9ZX0NCOworCQl5dXY0MjBfbW9kZSA9IHRydWU7CisJfQorCiAJLyogVkVO QyArIFZFTkMtRFZJIE1vZGUgc2V0dXAgKi8KLQltZXNvbl92ZW5jX2hkbWlfbW9kZV9zZXQocHJp diwgdmljLCBtb2RlKTsKKwltZXNvbl92ZW5jX2hkbWlfbW9kZV9zZXQocHJpdiwgdmljLCB5Y3Jj Yl9tYXAsIHl1djQyMF9tb2RlLCBtb2RlKTsKIAogCS8qIFZDTEsgU2V0IGNsb2NrICovCiAJZHdf aGRtaV9zZXRfdmNsayhkd19oZG1pLCBtb2RlKTsKIAotCS8qIFNldHVwIFlVVjQ0NCB0byBIRE1J LVRYLCBubyAxMGJpdCBkaXBoZXJpbmcgKi8KLQl3cml0ZWxfcmVsYXhlZCgwLCBwcml2LT5pb19i YXNlICsgX1JFRyhWUFVfSERNSV9GTVRfQ1RSTCkpOworCWlmIChkd19oZG1pLT5pbnB1dF9idXNf Zm9ybWF0ID09IE1FRElBX0JVU19GTVRfVVlZVllZOF8wXzVYMjQpCisJCS8qIFNldHVwIFlVVjQy MCB0byBIRE1JLVRYLCBubyAxMGJpdCBkaXBoZXJpbmcgKi8KKwkJd3JpdGVsX3JlbGF4ZWQoMiB8 ICgyIDw8IDIpLAorCQkJICAgICAgIHByaXYtPmlvX2Jhc2UgKyBfUkVHKFZQVV9IRE1JX0ZNVF9D VFJMKSk7CisJZWxzZQorCQkvKiBTZXR1cCBZVVY0NDQgdG8gSERNSS1UWCwgbm8gMTBiaXQgZGlw aGVyaW5nICovCisJCXdyaXRlbF9yZWxheGVkKDAsIHByaXYtPmlvX2Jhc2UgKyBfUkVHKFZQVV9I RE1JX0ZNVF9DVFJMKSk7CiB9CiAKIHN0YXRpYyBjb25zdCBzdHJ1Y3QgZHJtX2VuY29kZXJfaGVs cGVyX2Z1bmNzCkBAIC05NzcsNiArMTA0MCw3IEBAIHN0YXRpYyBpbnQgbWVzb25fZHdfaGRtaV9i aW5kKHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IGRldmljZSAqbWFzdGVyLAogCWR3X3BsYXRf ZGF0YS0+cGh5X2RhdGEgPSBtZXNvbl9kd19oZG1pOwogCWR3X3BsYXRfZGF0YS0+aW5wdXRfYnVz X2Zvcm1hdCA9IE1FRElBX0JVU19GTVRfWVVWOF8xWDI0OwogCWR3X3BsYXRfZGF0YS0+aW5wdXRf YnVzX2VuY29kaW5nID0gVjRMMl9ZQ0JDUl9FTkNfNzA5OworCWR3X3BsYXRfZGF0YS0+eWNiY3Jf NDIwX2FsbG93ZWQgPSB0cnVlOwogCiAJcGxhdGZvcm1fc2V0X2RydmRhdGEocGRldiwgbWVzb25f ZHdfaGRtaSk7CiAKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNvbl92Y2xr LmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25fdmNsay5jCmluZGV4IGIzOTAzNDc0NTQ0 NC4uNDQyNTBlZmY4YTNmIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25f dmNsay5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNvbl92Y2xrLmMKQEAgLTM2NCwx MiArMzY0LDE3IEBAIGVudW0gewogLyogMjk3MCAvMSAvMSAvMSAvNSAvMiAgPT4gLzEgLzEgKi8K IAlNRVNPTl9WQ0xLX0hETUlfMjk3MDAwLAogLyogNTk0MCAvMSAvMSAvMiAvNSAvMSAgPT4gLzEg LzEgKi8KLQlNRVNPTl9WQ0xLX0hETUlfNTk0MDAwCisJTUVTT05fVkNMS19IRE1JXzU5NDAwMCwK Ky8qIDI5NzAgLzEgLzEgLzEgLzUgLzEgID0+IC8xIC8yICovCisJTUVTT05fVkNMS19IRE1JXzU5 NDAwMF9ZVVY0MjAsCiB9OwogCiBzdHJ1Y3QgbWVzb25fdmNsa19wYXJhbXMgeworCXVuc2lnbmVk IGludCBwbGxfZnJlcTsKKwl1bnNpZ25lZCBpbnQgcGh5X2ZyZXE7CisJdW5zaWduZWQgaW50IHZj bGtfZnJlcTsKKwl1bnNpZ25lZCBpbnQgdmVuY19mcmVxOwogCXVuc2lnbmVkIGludCBwaXhlbF9m cmVxOwotCXVuc2lnbmVkIGludCBwbGxfYmFzZV9mcmVxOwogCXVuc2lnbmVkIGludCBwbGxfb2Qx OwogCXVuc2lnbmVkIGludCBwbGxfb2QyOwogCXVuc2lnbmVkIGludCBwbGxfb2QzOwpAQCAtMzc3 LDggKzM4MiwxMSBAQCBzdHJ1Y3QgbWVzb25fdmNsa19wYXJhbXMgewogCXVuc2lnbmVkIGludCB2 Y2xrX2RpdjsKIH0gcGFyYW1zW10gPSB7CiAJW01FU09OX1ZDTEtfSERNSV9FTkNJXzU0MDAwXSA9 IHsKKwkJLnBsbF9mcmVxID0gNDMyMDAwMCwKKwkJLnBoeV9mcmVxID0gMjcwMDAwLAorCQkudmNs a19mcmVxID0gNTQwMDAsCisJCS52ZW5jX2ZyZXEgPSA1NDAwMCwKIAkJLnBpeGVsX2ZyZXEgPSA1 NDAwMCwKLQkJLnBsbF9iYXNlX2ZyZXEgPSA0MzIwMDAwLAogCQkucGxsX29kMSA9IDQsCiAJCS5w bGxfb2QyID0gNCwKIAkJLnBsbF9vZDMgPSAxLApAQCAtMzg2LDggKzM5NCwxMSBAQCBzdHJ1Y3Qg bWVzb25fdmNsa19wYXJhbXMgewogCQkudmNsa19kaXYgPSAxLAogCX0sCiAJW01FU09OX1ZDTEtf SERNSV9ERFJfNTQwMDBdID0gewotCQkucGl4ZWxfZnJlcSA9IDU0MDAwLAotCQkucGxsX2Jhc2Vf ZnJlcSA9IDQzMjAwMDAsCisJCS5wbGxfZnJlcSA9IDQzMjAwMDAsCisJCS5waHlfZnJlcSA9IDI3 MDAwMCwKKwkJLnZjbGtfZnJlcSA9IDU0MDAwLAorCQkudmVuY19mcmVxID0gNTQwMDAsCisJCS5w aXhlbF9mcmVxID0gMjcwMDAsCiAJCS5wbGxfb2QxID0gNCwKIAkJLnBsbF9vZDIgPSA0LAogCQku cGxsX29kMyA9IDEsCkBAIC0zOTUsOCArNDA2LDExIEBAIHN0cnVjdCBtZXNvbl92Y2xrX3BhcmFt cyB7CiAJCS52Y2xrX2RpdiA9IDEsCiAJfSwKIAlbTUVTT05fVkNMS19IRE1JX0REUl8xNDg1MDBd ID0gewotCQkucGl4ZWxfZnJlcSA9IDE0ODUwMCwKLQkJLnBsbF9iYXNlX2ZyZXEgPSAyOTcwMDAw LAorCQkucGxsX2ZyZXEgPSAyOTcwMDAwLAorCQkucGh5X2ZyZXEgPSA3NDI1MDAsCisJCS52Y2xr X2ZyZXEgPSAxNDg1MDAsCisJCS52ZW5jX2ZyZXEgPSAxNDg1MDAsCisJCS5waXhlbF9mcmVxID0g NzQyNTAsCiAJCS5wbGxfb2QxID0gNCwKIAkJLnBsbF9vZDIgPSAxLAogCQkucGxsX29kMyA9IDEs CkBAIC00MDQsOCArNDE4LDExIEBAIHN0cnVjdCBtZXNvbl92Y2xrX3BhcmFtcyB7CiAJCS52Y2xr X2RpdiA9IDEsCiAJfSwKIAlbTUVTT05fVkNMS19IRE1JXzc0MjUwXSA9IHsKKwkJLnBsbF9mcmVx ID0gMjk3MDAwMCwKKwkJLnBoeV9mcmVxID0gNzQyNTAwLAorCQkudmNsa19mcmVxID0gNzQyNTAs CisJCS52ZW5jX2ZyZXEgPSA3NDI1MCwKIAkJLnBpeGVsX2ZyZXEgPSA3NDI1MCwKLQkJLnBsbF9i YXNlX2ZyZXEgPSAyOTcwMDAwLAogCQkucGxsX29kMSA9IDIsCiAJCS5wbGxfb2QyID0gMiwKIAkJ LnBsbF9vZDMgPSAyLApAQCAtNDEzLDggKzQzMCwxMSBAQCBzdHJ1Y3QgbWVzb25fdmNsa19wYXJh bXMgewogCQkudmNsa19kaXYgPSAxLAogCX0sCiAJW01FU09OX1ZDTEtfSERNSV8xNDg1MDBdID0g eworCQkucGxsX2ZyZXEgPSAyOTcwMDAwLAorCQkucGh5X2ZyZXEgPSAxNDg1MDAwLAorCQkudmNs a19mcmVxID0gMTQ4NTAwLAorCQkudmVuY19mcmVxID0gMTQ4NTAwLAogCQkucGl4ZWxfZnJlcSA9 IDE0ODUwMCwKLQkJLnBsbF9iYXNlX2ZyZXEgPSAyOTcwMDAwLAogCQkucGxsX29kMSA9IDEsCiAJ CS5wbGxfb2QyID0gMiwKIAkJLnBsbF9vZDMgPSAyLApAQCAtNDIyLDggKzQ0MiwxMSBAQCBzdHJ1 Y3QgbWVzb25fdmNsa19wYXJhbXMgewogCQkudmNsa19kaXYgPSAxLAogCX0sCiAJW01FU09OX1ZD TEtfSERNSV8yOTcwMDBdID0geworCQkucGxsX2ZyZXEgPSA1OTQwMDAwLAorCQkucGh5X2ZyZXEg PSAyOTcwMDAwLAorCQkudmVuY19mcmVxID0gMjk3MDAwLAorCQkudmNsa19mcmVxID0gMjk3MDAw LAogCQkucGl4ZWxfZnJlcSA9IDI5NzAwMCwKLQkJLnBsbF9iYXNlX2ZyZXEgPSA1OTQwMDAwLAog CQkucGxsX29kMSA9IDIsCiAJCS5wbGxfb2QyID0gMSwKIAkJLnBsbF9vZDMgPSAxLApAQCAtNDMx LDE0ICs0NTQsMjkgQEAgc3RydWN0IG1lc29uX3ZjbGtfcGFyYW1zIHsKIAkJLnZjbGtfZGl2ID0g MiwKIAl9LAogCVtNRVNPTl9WQ0xLX0hETUlfNTk0MDAwXSA9IHsKKwkJLnBsbF9mcmVxID0gNTk0 MDAwMCwKKwkJLnBoeV9mcmVxID0gNTk0MDAwMCwKKwkJLnZlbmNfZnJlcSA9IDU5NDAwMCwKKwkJ LnZjbGtfZnJlcSA9IDU5NDAwMCwKIAkJLnBpeGVsX2ZyZXEgPSA1OTQwMDAsCi0JCS5wbGxfYmFz ZV9mcmVxID0gNTk0MDAwMCwKIAkJLnBsbF9vZDEgPSAxLAogCQkucGxsX29kMiA9IDEsCiAJCS5w bGxfb2QzID0gMiwKIAkJLnZpZF9wbGxfZGl2ID0gVklEX1BMTF9ESVZfNSwKIAkJLnZjbGtfZGl2 ID0gMSwKIAl9LAorCVtNRVNPTl9WQ0xLX0hETUlfNTk0MDAwX1lVVjQyMF0gPSB7CisJCS5wbGxf ZnJlcSA9IDU5NDAwMDAsCisJCS5waHlfZnJlcSA9IDI5NzAwMDAsCisJCS52ZW5jX2ZyZXEgPSA1 OTQwMDAsCisJCS52Y2xrX2ZyZXEgPSA1OTQwMDAsCisJCS5waXhlbF9mcmVxID0gMjk3MDAwLAor CQkucGxsX29kMSA9IDIsCisJCS5wbGxfb2QyID0gMSwKKwkJLnBsbF9vZDMgPSAxLAorCQkudmlk X3BsbF9kaXYgPSBWSURfUExMX0RJVl81LAorCQkudmNsa19kaXYgPSAxLAorCX0sCiAJeyAvKiBz ZW50aW5lbCAqLyB9LAogfTsKIApAQCAtNjk2LDYgKzczNCw3IEBAIHN0YXRpYyB2b2lkIG1lc29u X2hkbWlfcGxsX2dlbmVyaWNfc2V0KHN0cnVjdCBtZXNvbl9kcm0gKnByaXYsCiAJdW5zaWduZWQg aW50IG9kLCBtLCBmcmFjLCBvZDEsIG9kMiwgb2QzOwogCiAJaWYgKG1lc29uX2hkbWlfcGxsX2Zp bmRfcGFyYW1zKHByaXYsIHBsbF9mcmVxLCAmbSwgJmZyYWMsICZvZCkpIHsKKwkJLyogT0QyIGdv ZXMgdG8gdGhlIFBIWSwgYW5kIG5lZWRzIHRvIGJlICoxMCwgc28ga2VlcCBPRDM9MSAqLwogCQlv ZDMgPSAxOwogCQlpZiAob2QgPCA0KSB7CiAJCQlvZDEgPSAyOwpAQCAtNzE4LDIxICs3NTcsMjgg QEAgc3RhdGljIHZvaWQgbWVzb25faGRtaV9wbGxfZ2VuZXJpY19zZXQoc3RydWN0IG1lc29uX2Ry bSAqcHJpdiwKIH0KIAogZW51bSBkcm1fbW9kZV9zdGF0dXMKLW1lc29uX3ZjbGtfdmljX3N1cHBv cnRlZF9mcmVxKHVuc2lnbmVkIGludCBmcmVxKQorbWVzb25fdmNsa192aWNfc3VwcG9ydGVkX2Zy ZXEodW5zaWduZWQgaW50IHBoeV9mcmVxLAorCQkJICAgICAgdW5zaWduZWQgaW50IHZjbGtfZnJl cSkKIHsKIAlpbnQgaTsKIAotCURSTV9ERUJVR19EUklWRVIoImZyZXEgPSAlZFxuIiwgZnJlcSk7 CisJRFJNX0RFQlVHX0RSSVZFUigicGh5X2ZyZXEgPSAlZCB2Y2xrX2ZyZXEgPSAlZFxuIiwKKwkJ CSBwaHlfZnJlcSwgdmNsa19mcmVxKTsKIAogCWZvciAoaSA9IDAgOyBwYXJhbXNbaV0ucGl4ZWxf ZnJlcSA7ICsraSkgewogCQlEUk1fREVCVUdfRFJJVkVSKCJpID0gJWQgcGl4ZWxfZnJlcSA9ICVk IGFsdCA9ICVkXG4iLAogCQkJCSBpLCBwYXJhbXNbaV0ucGl4ZWxfZnJlcSwKIAkJCQkgRlJFUV8x MDAwXzEwMDEocGFyYW1zW2ldLnBpeGVsX2ZyZXEpKTsKKwkJRFJNX0RFQlVHX0RSSVZFUigiaSA9 ICVkIHBoeV9mcmVxID0gJWQgYWx0ID0gJWRcbiIsCisJCQkJIGksIHBhcmFtc1tpXS5waHlfZnJl cSwKKwkJCQkgRlJFUV8xMDAwXzEwMDEocGFyYW1zW2ldLnBoeV9mcmVxLzEwKSoxMCk7CiAJCS8q IE1hdGNoIHN0cmljdCBmcmVxdWVuY3kgKi8KLQkJaWYgKGZyZXEgPT0gcGFyYW1zW2ldLnBpeGVs X2ZyZXEpCisJCWlmIChwaHlfZnJlcSA9PSBwYXJhbXNbaV0ucGh5X2ZyZXEgJiYKKwkJICAgIHZj bGtfZnJlcSA9PSBwYXJhbXNbaV0udmNsa19mcmVxKQogCQkJcmV0dXJuIE1PREVfT0s7CiAJCS8q IE1hdGNoIDEwMDAvMTAwMSB2YXJpYW50ICovCi0JCWlmIChmcmVxID09IEZSRVFfMTAwMF8xMDAx KHBhcmFtc1tpXS5waXhlbF9mcmVxKSkKKwkJaWYgKHBoeV9mcmVxID09IChGUkVRXzEwMDBfMTAw MShwYXJhbXNbaV0ucGh5X2ZyZXEvMTApKjEwKSAmJgorCQkgICAgdmNsa19mcmVxID09IEZSRVFf MTAwMF8xMDAxKHBhcmFtc1tpXS52Y2xrX2ZyZXEpKQogCQkJcmV0dXJuIE1PREVfT0s7CiAJfQog CkBAIC05NjAsOCArMTAwNiw5IEBAIHN0YXRpYyB2b2lkIG1lc29uX3ZjbGtfc2V0KHN0cnVjdCBt ZXNvbl9kcm0gKnByaXYsIHVuc2lnbmVkIGludCBwbGxfYmFzZV9mcmVxLAogfQogCiB2b2lkIG1l c29uX3ZjbGtfc2V0dXAoc3RydWN0IG1lc29uX2RybSAqcHJpdiwgdW5zaWduZWQgaW50IHRhcmdl dCwKLQkJICAgICAgdW5zaWduZWQgaW50IHZjbGtfZnJlcSwgdW5zaWduZWQgaW50IHZlbmNfZnJl cSwKLQkJICAgICAgdW5zaWduZWQgaW50IGRhY19mcmVxLCBib29sIGhkbWlfdXNlX2VuY2kpCisJ CSAgICAgIHVuc2lnbmVkIGludCBwaHlfZnJlcSwgdW5zaWduZWQgaW50IHZjbGtfZnJlcSwKKwkJ ICAgICAgdW5zaWduZWQgaW50IHZlbmNfZnJlcSwgdW5zaWduZWQgaW50IGRhY19mcmVxLAorCQkg ICAgICBib29sIGhkbWlfdXNlX2VuY2kpCiB7CiAJYm9vbCB2aWNfYWx0ZXJuYXRlX2Nsb2NrID0g ZmFsc2U7CiAJdW5zaWduZWQgaW50IGZyZXE7CkBAIC05ODAsNyArMTAyNyw3IEBAIHZvaWQgbWVz b25fdmNsa19zZXR1cChzdHJ1Y3QgbWVzb25fZHJtICpwcml2LCB1bnNpZ25lZCBpbnQgdGFyZ2V0 LAogCQkgKiAtIHZlbmNfZGl2ID0gMQogCQkgKiAtIGVuY3AgZW5jb2RlcgogCQkgKi8KLQkJbWVz b25fdmNsa19zZXQocHJpdiwgdmNsa19mcmVxICogMTAsIDAsIDAsIDAsCisJCW1lc29uX3ZjbGtf c2V0KHByaXYsIHBoeV9mcmVxLCAwLCAwLCAwLAogCQkJICAgICAgIFZJRF9QTExfRElWXzUsIDIs IDEsIDEsIGZhbHNlLCBmYWxzZSk7CiAJCXJldHVybjsKIAl9CkBAIC0xMDAyLDkgKzEwNDksMTEg QEAgdm9pZCBtZXNvbl92Y2xrX3NldHVwKHN0cnVjdCBtZXNvbl9kcm0gKnByaXYsIHVuc2lnbmVk IGludCB0YXJnZXQsCiAJfQogCiAJZm9yIChmcmVxID0gMCA7IHBhcmFtc1tmcmVxXS5waXhlbF9m cmVxIDsgKytmcmVxKSB7Ci0JCWlmICh2Y2xrX2ZyZXEgPT0gcGFyYW1zW2ZyZXFdLnBpeGVsX2Zy ZXEgfHwKLQkJICAgIHZjbGtfZnJlcSA9PSBGUkVRXzEwMDBfMTAwMShwYXJhbXNbZnJlcV0ucGl4 ZWxfZnJlcSkpIHsKLQkJCWlmICh2Y2xrX2ZyZXEgIT0gcGFyYW1zW2ZyZXFdLnBpeGVsX2ZyZXEp CisJCWlmICgocGh5X2ZyZXEgPT0gcGFyYW1zW2ZyZXFdLnBoeV9mcmVxIHx8CisJCSAgICAgcGh5 X2ZyZXEgPT0gRlJFUV8xMDAwXzEwMDEocGFyYW1zW2ZyZXFdLnBoeV9mcmVxLzEwKSoxMCkgJiYK KwkJICAgICh2Y2xrX2ZyZXEgPT0gcGFyYW1zW2ZyZXFdLnZjbGtfZnJlcSB8fAorCQkgICAgIHZj bGtfZnJlcSA9PSBGUkVRXzEwMDBfMTAwMShwYXJhbXNbZnJlcV0udmNsa19mcmVxKSkpIHsKKwkJ CWlmICh2Y2xrX2ZyZXEgIT0gcGFyYW1zW2ZyZXFdLnZjbGtfZnJlcSkKIAkJCQl2aWNfYWx0ZXJu YXRlX2Nsb2NrID0gdHJ1ZTsKIAkJCWVsc2UKIAkJCQl2aWNfYWx0ZXJuYXRlX2Nsb2NrID0gZmFs c2U7CkBAIC0xMDMzLDcgKzEwODIsNyBAQCB2b2lkIG1lc29uX3ZjbGtfc2V0dXAoc3RydWN0IG1l c29uX2RybSAqcHJpdiwgdW5zaWduZWQgaW50IHRhcmdldCwKIAkJcmV0dXJuOwogCX0KIAotCW1l c29uX3ZjbGtfc2V0KHByaXYsIHBhcmFtc1tmcmVxXS5wbGxfYmFzZV9mcmVxLAorCW1lc29uX3Zj bGtfc2V0KHByaXYsIHBhcmFtc1tmcmVxXS5wbGxfZnJlcSwKIAkJICAgICAgIHBhcmFtc1tmcmVx XS5wbGxfb2QxLCBwYXJhbXNbZnJlcV0ucGxsX29kMiwKIAkJICAgICAgIHBhcmFtc1tmcmVxXS5w bGxfb2QzLCBwYXJhbXNbZnJlcV0udmlkX3BsbF9kaXYsCiAJCSAgICAgICBwYXJhbXNbZnJlcV0u dmNsa19kaXYsIGhkbWlfdHhfZGl2LCB2ZW5jX2RpdiwKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1 L2RybS9tZXNvbi9tZXNvbl92Y2xrLmggYi9kcml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25fdmNs ay5oCmluZGV4IDRiZDg3NTJkYTAyYS4uYzRkMTlkZGZjZDc5IDEwMDY0NAotLS0gYS9kcml2ZXJz L2dwdS9kcm0vbWVzb24vbWVzb25fdmNsay5oCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9tZXNvbi9t ZXNvbl92Y2xrLmgKQEAgLTMzLDEwICszMywxMSBAQCBlbnVtIHsKIGVudW0gZHJtX21vZGVfc3Rh dHVzCiBtZXNvbl92Y2xrX2RtdF9zdXBwb3J0ZWRfZnJlcShzdHJ1Y3QgbWVzb25fZHJtICpwcml2 LCB1bnNpZ25lZCBpbnQgZnJlcSk7CiBlbnVtIGRybV9tb2RlX3N0YXR1cwotbWVzb25fdmNsa192 aWNfc3VwcG9ydGVkX2ZyZXEodW5zaWduZWQgaW50IGZyZXEpOworbWVzb25fdmNsa192aWNfc3Vw cG9ydGVkX2ZyZXEodW5zaWduZWQgaW50IHBoeV9mcmVxLCB1bnNpZ25lZCBpbnQgdmNsa19mcmVx KTsKIAogdm9pZCBtZXNvbl92Y2xrX3NldHVwKHN0cnVjdCBtZXNvbl9kcm0gKnByaXYsIHVuc2ln bmVkIGludCB0YXJnZXQsCi0JCSAgICAgIHVuc2lnbmVkIGludCB2Y2xrX2ZyZXEsIHVuc2lnbmVk IGludCB2ZW5jX2ZyZXEsCi0JCSAgICAgIHVuc2lnbmVkIGludCBkYWNfZnJlcSwgYm9vbCBoZG1p X3VzZV9lbmNpKTsKKwkJICAgICAgdW5zaWduZWQgaW50IHBoeV9mcmVxLCB1bnNpZ25lZCBpbnQg dmNsa19mcmVxLAorCQkgICAgICB1bnNpZ25lZCBpbnQgdmVuY19mcmVxLCB1bnNpZ25lZCBpbnQg ZGFjX2ZyZXEsCisJCSAgICAgIGJvb2wgaGRtaV91c2VfZW5jaSk7CiAKICNlbmRpZiAvKiBfX01F U09OX1ZDTEtfSCAqLwpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX3Zl bmMuYyBiL2RyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNvbl92ZW5jLmMKaW5kZXggNmZhY2E3MzEz MzM5Li41NDYwYzQ0Mzk2MTIgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNv bl92ZW5jLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX3ZlbmMuYwpAQCAtOTU4 LDYgKzk1OCw4IEBAIGJvb2wgbWVzb25fdmVuY19oZG1pX3ZlbmNfcmVwZWF0KGludCB2aWMpCiBF WFBPUlRfU1lNQk9MX0dQTChtZXNvbl92ZW5jX2hkbWlfdmVuY19yZXBlYXQpOwogCiB2b2lkIG1l c29uX3ZlbmNfaGRtaV9tb2RlX3NldChzdHJ1Y3QgbWVzb25fZHJtICpwcml2LCBpbnQgdmljLAor CQkJICAgICAgdW5zaWduZWQgaW50IHljcmNiX21hcCwKKwkJCSAgICAgIGJvb2wgeXV2NDIwX21v ZGUsCiAJCQkgICAgICBzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAqbW9kZSkKIHsKIAl1bmlvbiBt ZXNvbl9oZG1pX3ZlbmNfbW9kZSAqdm1vZGUgPSBOVUxMOwpAQCAtMTUwOCw4ICsxNTEwLDggQEAg dm9pZCBtZXNvbl92ZW5jX2hkbWlfbW9kZV9zZXQoc3RydWN0IG1lc29uX2RybSAqcHJpdiwgaW50 IHZpYywKIAl3cml0ZWxfcmVsYXhlZCgodXNlX2VuY2kgPyAxIDogMikgfAogCQkgICAgICAgKG1v ZGUtPmZsYWdzICYgRFJNX01PREVfRkxBR19QSFNZTkMgPyAxIDw8IDIgOiAwKSB8CiAJCSAgICAg ICAobW9kZS0+ZmxhZ3MgJiBEUk1fTU9ERV9GTEFHX1BWU1lOQyA/IDEgPDwgMyA6IDApIHwKLQkJ ICAgICAgIDQgPDwgNSB8Ci0JCSAgICAgICAodmVuY19yZXBlYXQgPyAxIDw8IDggOiAwKSB8CisJ CSAgICAgICAoeWNyY2JfbWFwIDw8IDUpIHwKKwkJICAgICAgICh2ZW5jX3JlcGVhdCB8fCB5dXY0 MjBfbW9kZSA/IDEgPDwgOCA6IDApIHwKIAkJICAgICAgIChoZG1pX3JlcGVhdCA/IDEgPDwgMTIg OiAwKSwKIAkJICAgICAgIHByaXYtPmlvX2Jhc2UgKyBfUkVHKFZQVV9IRE1JX1NFVFRJTkcpKTsK IApkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX3ZlbmMuaCBiL2RyaXZl cnMvZ3B1L2RybS9tZXNvbi9tZXNvbl92ZW5jLmgKaW5kZXggOTdlYWViYmZhMGM0Li41NTgwYmYz OGUzODEgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNvbl92ZW5jLmgKKysr IGIvZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX3ZlbmMuaApAQCAtMzMsNiArMzMsMTUgQEAg ZW51bSB7CiAJTUVTT05fVkVOQ19NT0RFX0hETUksCiB9OwogCitlbnVtIHsKKwlNRVNPTl9WRU5D X01BUF9DUl9ZX0NCID0gMCwKKwlNRVNPTl9WRU5DX01BUF9ZX0NCX0NSLAorCU1FU09OX1ZFTkNf TUFQX1lfQ1JfQ0IsCisJTUVTT05fVkVOQ19NQVBfQ0JfQ1JfWSwKKwlNRVNPTl9WRU5DX01BUF9D Ql9ZX0NSLAorCU1FU09OX1ZFTkNfTUFQX0NSX0NCX1ksCit9OworCiBzdHJ1Y3QgbWVzb25fY3Zi c19lbmNpX21vZGUgewogCXVuc2lnbmVkIGludCBtb2RlX3RhZzsKIAl1bnNpZ25lZCBpbnQgaHNv X2JlZ2luOyAvKiBIU08gYmVnaW4gcG9zaXRpb24gKi8KQEAgLTcwLDYgKzc5LDggQEAgZXh0ZXJu IHN0cnVjdCBtZXNvbl9jdmJzX2VuY2lfbW9kZSBtZXNvbl9jdmJzX2VuY2lfbnRzYzsKIHZvaWQg bWVzb25fdmVuY2lfY3Zic19tb2RlX3NldChzdHJ1Y3QgbWVzb25fZHJtICpwcml2LAogCQkJICAg ICAgIHN0cnVjdCBtZXNvbl9jdmJzX2VuY2lfbW9kZSAqbW9kZSk7CiB2b2lkIG1lc29uX3ZlbmNf aGRtaV9tb2RlX3NldChzdHJ1Y3QgbWVzb25fZHJtICpwcml2LCBpbnQgdmljLAorCQkJICAgICAg dW5zaWduZWQgaW50IHljcmNiX21hcCwKKwkJCSAgICAgIGJvb2wgeXV2NDIwX21vZGUsCiAJCQkg ICAgICBzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAqbW9kZSk7CiB1bnNpZ25lZCBpbnQgbWVzb25f dmVuY2lfZ2V0X2ZpZWxkKHN0cnVjdCBtZXNvbl9kcm0gKnByaXYpOwogCmRpZmYgLS1naXQgYS9k cml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25fdmVuY19jdmJzLmMgYi9kcml2ZXJzL2dwdS9kcm0v bWVzb24vbWVzb25fdmVuY19jdmJzLmMKaW5kZXggMmM1MzQxYzg4MWM0Li5jMWJiYzYwMWNmMTMg MTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNvbl92ZW5jX2N2YnMuYworKysg Yi9kcml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25fdmVuY19jdmJzLmMKQEAgLTIxOCw3ICsyMTgs OCBAQCBzdGF0aWMgdm9pZCBtZXNvbl92ZW5jX2N2YnNfZW5jb2Rlcl9tb2RlX3NldChzdHJ1Y3Qg ZHJtX2VuY29kZXIgKmVuY29kZXIsCiAJCQkvKiBTZXR1cCAyN01IeiB2Y2xrMiBmb3IgRU5DSSBh bmQgVkRBQyAqLwogCQkJbWVzb25fdmNsa19zZXR1cChwcml2LCBNRVNPTl9WQ0xLX1RBUkdFVF9D VkJTLAogCQkJCQkgTUVTT05fVkNMS19DVkJTLCBNRVNPTl9WQ0xLX0NWQlMsCi0JCQkJCSBNRVNP Tl9WQ0xLX0NWQlMsIHRydWUpOworCQkJCQkgTUVTT05fVkNMS19DVkJTLCBNRVNPTl9WQ0xLX0NW QlMsCisJCQkJCSB0cnVlKTsKIAkJCWJyZWFrOwogCQl9CiAJfQotLSAKMi4yMS4wCgpfX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGlu ZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVl ZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWw= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C018EC04E87 for ; Mon, 20 May 2019 13:38:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 76DBD20856 for ; Mon, 20 May 2019 13:38:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="Dkz9NX5I" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389155AbfETNiP (ORCPT ); Mon, 20 May 2019 09:38:15 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:37937 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388675AbfETNiE (ORCPT ); Mon, 20 May 2019 09:38:04 -0400 Received: by mail-wm1-f65.google.com with SMTP id t5so11732111wmh.3 for ; Mon, 20 May 2019 06:38:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MZ9lTWI+Lc/C+oK4npZx3sJLpiEnZG/zd/AYB4si+t8=; b=Dkz9NX5IhZv8/njLB0RdVNKRYnHa9zrgXGtpigEfsfXpFkTycOX2nFKMU9jIygylDX btHlra31XFxIEiN7N5StNn8jsrEG3BUm/Bgf4Bz0rizMyQZtMEp5uSJUYt0vOJTd0a41 tlTX7oQu/31UR2r42+cyddgrglS9F2j6m7Tvjn8n7Hnor2w4Kp7M81HUayar6cna0ln7 aOp+qq3JQugEW8eo+W9WyjTF7XbwU3FOwAzmw0HmcagS94zixdFj15Y6cCPT+z7rJeb3 xFh11xoNyCK1qL4cr3bTgzJkGAdHcdNa3G14KbhkWkgDCo5EctlNtNsO6czXYyNxvXgZ ttLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MZ9lTWI+Lc/C+oK4npZx3sJLpiEnZG/zd/AYB4si+t8=; b=DNXGHx3LuS18prPWFQ2EE6Pzju6oCAi1Qtrs8iuJgHLoCMnxh67/JjXre4dwFjn5Wc YzQWDovo1ScLJF5rPGrRGYrwHfd/TugG8UC4D61q6fYTecp/ymP83tn9gYW7pbX1hhmd 5ecRkl+7nbFZGxw/C66UHOQdgyUaS/9nfN/Mfzu4eAlytLLzaFQ4x/1vb2oUp8Kz3KkH edBSWfgTd4YhhxluDUEJdbiXpmAhrEKIBKDOhmGzz50rcWdGpWLrrif21SrwMlmoDVu0 8etq+nD86sQ+sCv+srBMj7kZsYYCf7XAtNkxcRsWpBdlmRcJ6I7RnHIpB9dMxN1mt3FV 0png== X-Gm-Message-State: APjAAAU4q1bbR4CylmSqCeLdFLpocU2+Q0IDgD/iIZTKikGmd/98UT3U i3u9uyrtA3Jj8Ej8e9skhGkOcw== X-Google-Smtp-Source: APXvYqxa5RaiIeHtqDyp7p2Aeh02OdD024JHejqByLNaNF33pGnOdgb4OUGNF/0uxiMAQY8Wau1bKg== X-Received: by 2002:a1c:cb81:: with SMTP id b123mr11978006wmg.107.1558359481053; Mon, 20 May 2019 06:38:01 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id t19sm12167059wmi.42.2019.05.20.06.37.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 May 2019 06:38:00 -0700 (PDT) From: Neil Armstrong To: a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com Cc: jonas@kwiboo.se, hverkuil@xs4all.nl, Neil Armstrong , dri-devel@lists.freedesktop.org, jernej.skrabec@siol.net, heiko@sntech.de, maxime.ripard@bootlin.com, hjc@rock-chips.com, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] drm/meson: Add YUV420 output support Date: Mon, 20 May 2019 15:37:52 +0200 Message-Id: <20190520133753.23871-5-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190520133753.23871-1-narmstrong@baylibre.com> References: <20190520133753.23871-1-narmstrong@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support for the YUV420 output from the Amlogic Meson SoCs Video Processing Unit to the HDMI Controller. The YUV420 is obtained by generating a YUV444 pixel stream like the classic HDMI display modes, but then the Video Encoder output can be configured to down-sample the YUV444 pixel stream to a YUV420 stream. In addition if pixel stream down-sampling, the Y Cb Cr components must also be mapped differently to align with the HDMI2.0 specifications. This mode needs a different clock generation scheme since the TMDS PHY clock must match the 10x ration with the YUV420 pixel clock, but the video encoder must run at 2x the pixel clock. This patch adds the TMDS PHY clock value in all the video clock setup in order to better support these specific uses cases and switch to the Common Clock framework for clocks handling in the future. When 420 is needed, it calls drm_bridge_format_set() for notify the bridge the input format has changed to YUV420. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_dw_hdmi.c | 100 +++++++++++++++++++----- drivers/gpu/drm/meson/meson_vclk.c | 93 ++++++++++++++++------ drivers/gpu/drm/meson/meson_vclk.h | 7 +- drivers/gpu/drm/meson/meson_venc.c | 6 +- drivers/gpu/drm/meson/meson_venc.h | 11 +++ drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- 6 files changed, 174 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index 779da21143b9..5d67e2beba58 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -159,6 +159,7 @@ struct meson_dw_hdmi { struct regulator *hdmi_supply; u32 irq_stat; struct dw_hdmi *hdmi; + unsigned long input_bus_format; }; #define encoder_to_meson_dw_hdmi(x) \ container_of(x, struct meson_dw_hdmi, encoder) @@ -308,6 +309,10 @@ static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi, struct meson_drm *priv = dw_hdmi->priv; unsigned int pixel_clock = mode->clock; + /* For 420, pixel clock is half unlike venc clock */ + if (dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24) + pixel_clock /= 2; + if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) { if (pixel_clock >= 371250) { @@ -383,25 +388,36 @@ static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi, { struct meson_drm *priv = dw_hdmi->priv; int vic = drm_match_cea_mode(mode); + unsigned int phy_freq; unsigned int vclk_freq; unsigned int venc_freq; unsigned int hdmi_freq; vclk_freq = mode->clock; + /* For 420, pixel clock is half unlike venc clock */ + if (dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24) + vclk_freq /= 2; + + /* TMDS clock is pixel_clock * 10 */ + phy_freq = vclk_freq * 10; + if (!vic) { - meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, vclk_freq, - vclk_freq, vclk_freq, false); + meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, phy_freq, + vclk_freq, vclk_freq, vclk_freq, false); return; } + /* 480i/576i needs global pixel doubling */ if (mode->flags & DRM_MODE_FLAG_DBLCLK) vclk_freq *= 2; venc_freq = vclk_freq; hdmi_freq = vclk_freq; - if (meson_venc_hdmi_venc_repeat(vic)) + /* VENC double pixels for 1080i, 720p and YUV420 modes */ + if (meson_venc_hdmi_venc_repeat(vic) || + dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24) venc_freq *= 2; vclk_freq = max(venc_freq, hdmi_freq); @@ -409,11 +425,11 @@ static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi, if (mode->flags & DRM_MODE_FLAG_DBLCLK) venc_freq /= 2; - DRM_DEBUG_DRIVER("vclk:%d venc=%d hdmi=%d enci=%d\n", - vclk_freq, venc_freq, hdmi_freq, + DRM_DEBUG_DRIVER("vclk:%d phy=%d venc=%d hdmi=%d enci=%d\n", + phy_freq, vclk_freq, venc_freq, hdmi_freq, priv->venc.hdmi_use_enci); - meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, vclk_freq, + meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, phy_freq, vclk_freq, venc_freq, hdmi_freq, priv->venc.hdmi_use_enci); } @@ -446,8 +462,9 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, /* Enable normal output to PHY */ dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12)); - /* TMDS pattern setup (TOFIX Handle the YUV420 case) */ - if (mode->clock > 340000) { + /* TMDS pattern setup */ + if (mode->clock > 340000 && + dw_hdmi->input_bus_format == MEDIA_BUS_FMT_YUV8_1X24) { dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0); dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, @@ -622,6 +639,8 @@ dw_hdmi_mode_valid(struct drm_connector *connector, const struct drm_display_mode *mode) { struct meson_drm *priv = connector->dev->dev_private; + bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported; + unsigned int phy_freq; unsigned int vclk_freq; unsigned int venc_freq; unsigned int hdmi_freq; @@ -630,9 +649,11 @@ dw_hdmi_mode_valid(struct drm_connector *connector, DRM_DEBUG_DRIVER("Modeline " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); - /* If sink max TMDS clock, we reject the mode */ + /* If sink does not support 540MHz, reject the non-420 HDMI2 modes */ if (connector->display_info.max_tmds_clock && - mode->clock > connector->display_info.max_tmds_clock) + mode->clock > connector->display_info.max_tmds_clock && + !drm_mode_is_420_only(&connector->display_info, mode) && + !drm_mode_is_420_also(&connector->display_info, mode)) return MODE_BAD; /* Check against non-VIC supported modes */ @@ -648,6 +669,15 @@ dw_hdmi_mode_valid(struct drm_connector *connector, vclk_freq = mode->clock; + /* For 420, pixel clock is half unlike venc clock */ + if (drm_mode_is_420_only(&connector->display_info, mode) || + (!is_hdmi2_sink && + drm_mode_is_420_also(&connector->display_info, mode))) + vclk_freq /= 2; + + /* TMDS clock is pixel_clock * 10 */ + phy_freq = vclk_freq * 10; + /* 480i/576i needs global pixel doubling */ if (mode->flags & DRM_MODE_FLAG_DBLCLK) vclk_freq *= 2; @@ -655,8 +685,11 @@ dw_hdmi_mode_valid(struct drm_connector *connector, venc_freq = vclk_freq; hdmi_freq = vclk_freq; - /* VENC double pixels for 1080i and 720p modes */ - if (meson_venc_hdmi_venc_repeat(vic)) + /* VENC double pixels for 1080i, 720p and YUV420 modes */ + if (meson_venc_hdmi_venc_repeat(vic) || + drm_mode_is_420_only(&connector->display_info, mode) || + (!is_hdmi2_sink && + drm_mode_is_420_also(&connector->display_info, mode))) venc_freq *= 2; vclk_freq = max(venc_freq, hdmi_freq); @@ -664,10 +697,10 @@ dw_hdmi_mode_valid(struct drm_connector *connector, if (mode->flags & DRM_MODE_FLAG_DBLCLK) venc_freq /= 2; - dev_dbg(connector->dev->dev, "%s: vclk:%d venc=%d hdmi=%d\n", __func__, - vclk_freq, venc_freq, hdmi_freq); + dev_dbg(connector->dev->dev, "%s: vclk:%d phy=%d venc=%d hdmi=%d\n", + __func__, phy_freq, vclk_freq, venc_freq, hdmi_freq); - return meson_vclk_vic_supported_freq(vclk_freq); + return meson_vclk_vic_supported_freq(phy_freq, vclk_freq); } /* Encoder */ @@ -685,6 +718,24 @@ static int meson_venc_hdmi_encoder_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); + struct drm_display_info *info = &conn_state->connector->display_info; + struct drm_display_mode *mode = &crtc_state->mode; + bool is_hdmi2_sink = + conn_state->connector->display_info.hdmi.scdc.supported; + + if (drm_mode_is_420_only(info, mode) || + (!is_hdmi2_sink && drm_mode_is_420_also(info, mode))) + dw_hdmi->input_bus_format = MEDIA_BUS_FMT_UYYVYY8_0_5X24; + else + dw_hdmi->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24; + + /* Specify the encoder output format to the bridge */ + if (!drm_bridge_format_set(encoder->bridge, + dw_hdmi->input_bus_format, + V4L2_YCBCR_ENC_709)) + return -EINVAL; + return 0; } @@ -722,17 +773,29 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder *encoder, struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); struct meson_drm *priv = dw_hdmi->priv; int vic = drm_match_cea_mode(mode); + unsigned int ycrcb_map = MESON_VENC_MAP_CB_Y_CR; + bool yuv420_mode = false; DRM_DEBUG_DRIVER("\"%s\" vic %d\n", mode->name, vic); + if (dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24) { + ycrcb_map = MESON_VENC_MAP_CR_Y_CB; + yuv420_mode = true; + } + /* VENC + VENC-DVI Mode setup */ - meson_venc_hdmi_mode_set(priv, vic, mode); + meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, yuv420_mode, mode); /* VCLK Set clock */ dw_hdmi_set_vclk(dw_hdmi, mode); - /* Setup YUV444 to HDMI-TX, no 10bit diphering */ - writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); + if (dw_hdmi->input_bus_format == MEDIA_BUS_FMT_UYYVYY8_0_5X24) + /* Setup YUV420 to HDMI-TX, no 10bit diphering */ + writel_relaxed(2 | (2 << 2), + priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); + else + /* Setup YUV444 to HDMI-TX, no 10bit diphering */ + writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); } static const struct drm_encoder_helper_funcs @@ -977,6 +1040,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master, dw_plat_data->phy_data = meson_dw_hdmi; dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24; dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709; + dw_plat_data->ycbcr_420_allowed = true; platform_set_drvdata(pdev, meson_dw_hdmi); diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c index b39034745444..44250eff8a3f 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -364,12 +364,17 @@ enum { /* 2970 /1 /1 /1 /5 /2 => /1 /1 */ MESON_VCLK_HDMI_297000, /* 5940 /1 /1 /2 /5 /1 => /1 /1 */ - MESON_VCLK_HDMI_594000 + MESON_VCLK_HDMI_594000, +/* 2970 /1 /1 /1 /5 /1 => /1 /2 */ + MESON_VCLK_HDMI_594000_YUV420, }; struct meson_vclk_params { + unsigned int pll_freq; + unsigned int phy_freq; + unsigned int vclk_freq; + unsigned int venc_freq; unsigned int pixel_freq; - unsigned int pll_base_freq; unsigned int pll_od1; unsigned int pll_od2; unsigned int pll_od3; @@ -377,8 +382,11 @@ struct meson_vclk_params { unsigned int vclk_div; } params[] = { [MESON_VCLK_HDMI_ENCI_54000] = { + .pll_freq = 4320000, + .phy_freq = 270000, + .vclk_freq = 54000, + .venc_freq = 54000, .pixel_freq = 54000, - .pll_base_freq = 4320000, .pll_od1 = 4, .pll_od2 = 4, .pll_od3 = 1, @@ -386,8 +394,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_DDR_54000] = { - .pixel_freq = 54000, - .pll_base_freq = 4320000, + .pll_freq = 4320000, + .phy_freq = 270000, + .vclk_freq = 54000, + .venc_freq = 54000, + .pixel_freq = 27000, .pll_od1 = 4, .pll_od2 = 4, .pll_od3 = 1, @@ -395,8 +406,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_DDR_148500] = { - .pixel_freq = 148500, - .pll_base_freq = 2970000, + .pll_freq = 2970000, + .phy_freq = 742500, + .vclk_freq = 148500, + .venc_freq = 148500, + .pixel_freq = 74250, .pll_od1 = 4, .pll_od2 = 1, .pll_od3 = 1, @@ -404,8 +418,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_74250] = { + .pll_freq = 2970000, + .phy_freq = 742500, + .vclk_freq = 74250, + .venc_freq = 74250, .pixel_freq = 74250, - .pll_base_freq = 2970000, .pll_od1 = 2, .pll_od2 = 2, .pll_od3 = 2, @@ -413,8 +430,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_148500] = { + .pll_freq = 2970000, + .phy_freq = 1485000, + .vclk_freq = 148500, + .venc_freq = 148500, .pixel_freq = 148500, - .pll_base_freq = 2970000, .pll_od1 = 1, .pll_od2 = 2, .pll_od3 = 2, @@ -422,8 +442,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_297000] = { + .pll_freq = 5940000, + .phy_freq = 2970000, + .venc_freq = 297000, + .vclk_freq = 297000, .pixel_freq = 297000, - .pll_base_freq = 5940000, .pll_od1 = 2, .pll_od2 = 1, .pll_od3 = 1, @@ -431,14 +454,29 @@ struct meson_vclk_params { .vclk_div = 2, }, [MESON_VCLK_HDMI_594000] = { + .pll_freq = 5940000, + .phy_freq = 5940000, + .venc_freq = 594000, + .vclk_freq = 594000, .pixel_freq = 594000, - .pll_base_freq = 5940000, .pll_od1 = 1, .pll_od2 = 1, .pll_od3 = 2, .vid_pll_div = VID_PLL_DIV_5, .vclk_div = 1, }, + [MESON_VCLK_HDMI_594000_YUV420] = { + .pll_freq = 5940000, + .phy_freq = 2970000, + .venc_freq = 594000, + .vclk_freq = 594000, + .pixel_freq = 297000, + .pll_od1 = 2, + .pll_od2 = 1, + .pll_od3 = 1, + .vid_pll_div = VID_PLL_DIV_5, + .vclk_div = 1, + }, { /* sentinel */ }, }; @@ -696,6 +734,7 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv, unsigned int od, m, frac, od1, od2, od3; if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) { + /* OD2 goes to the PHY, and needs to be *10, so keep OD3=1 */ od3 = 1; if (od < 4) { od1 = 2; @@ -718,21 +757,28 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv, } enum drm_mode_status -meson_vclk_vic_supported_freq(unsigned int freq) +meson_vclk_vic_supported_freq(unsigned int phy_freq, + unsigned int vclk_freq) { int i; - DRM_DEBUG_DRIVER("freq = %d\n", freq); + DRM_DEBUG_DRIVER("phy_freq = %d vclk_freq = %d\n", + phy_freq, vclk_freq); for (i = 0 ; params[i].pixel_freq ; ++i) { DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n", i, params[i].pixel_freq, FREQ_1000_1001(params[i].pixel_freq)); + DRM_DEBUG_DRIVER("i = %d phy_freq = %d alt = %d\n", + i, params[i].phy_freq, + FREQ_1000_1001(params[i].phy_freq/10)*10); /* Match strict frequency */ - if (freq == params[i].pixel_freq) + if (phy_freq == params[i].phy_freq && + vclk_freq == params[i].vclk_freq) return MODE_OK; /* Match 1000/1001 variant */ - if (freq == FREQ_1000_1001(params[i].pixel_freq)) + if (phy_freq == (FREQ_1000_1001(params[i].phy_freq/10)*10) && + vclk_freq == FREQ_1000_1001(params[i].vclk_freq)) return MODE_OK; } @@ -960,8 +1006,9 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq, } void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int vclk_freq, unsigned int venc_freq, - unsigned int dac_freq, bool hdmi_use_enci) + unsigned int phy_freq, unsigned int vclk_freq, + unsigned int venc_freq, unsigned int dac_freq, + bool hdmi_use_enci) { bool vic_alternate_clock = false; unsigned int freq; @@ -980,7 +1027,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, * - venc_div = 1 * - encp encoder */ - meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0, + meson_vclk_set(priv, phy_freq, 0, 0, 0, VID_PLL_DIV_5, 2, 1, 1, false, false); return; } @@ -1002,9 +1049,11 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, } for (freq = 0 ; params[freq].pixel_freq ; ++freq) { - if (vclk_freq == params[freq].pixel_freq || - vclk_freq == FREQ_1000_1001(params[freq].pixel_freq)) { - if (vclk_freq != params[freq].pixel_freq) + if ((phy_freq == params[freq].phy_freq || + phy_freq == FREQ_1000_1001(params[freq].phy_freq/10)*10) && + (vclk_freq == params[freq].vclk_freq || + vclk_freq == FREQ_1000_1001(params[freq].vclk_freq))) { + if (vclk_freq != params[freq].vclk_freq) vic_alternate_clock = true; else vic_alternate_clock = false; @@ -1033,7 +1082,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, return; } - meson_vclk_set(priv, params[freq].pll_base_freq, + meson_vclk_set(priv, params[freq].pll_freq, params[freq].pll_od1, params[freq].pll_od2, params[freq].pll_od3, params[freq].vid_pll_div, params[freq].vclk_div, hdmi_tx_div, venc_div, diff --git a/drivers/gpu/drm/meson/meson_vclk.h b/drivers/gpu/drm/meson/meson_vclk.h index 4bd8752da02a..c4d19ddfcd79 100644 --- a/drivers/gpu/drm/meson/meson_vclk.h +++ b/drivers/gpu/drm/meson/meson_vclk.h @@ -33,10 +33,11 @@ enum { enum drm_mode_status meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq); enum drm_mode_status -meson_vclk_vic_supported_freq(unsigned int freq); +meson_vclk_vic_supported_freq(unsigned int phy_freq, unsigned int vclk_freq); void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int vclk_freq, unsigned int venc_freq, - unsigned int dac_freq, bool hdmi_use_enci); + unsigned int phy_freq, unsigned int vclk_freq, + unsigned int venc_freq, unsigned int dac_freq, + bool hdmi_use_enci); #endif /* __MESON_VCLK_H */ diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c index 6faca7313339..5460c4439612 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -958,6 +958,8 @@ bool meson_venc_hdmi_venc_repeat(int vic) EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat); void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, + unsigned int ycrcb_map, + bool yuv420_mode, struct drm_display_mode *mode) { union meson_hdmi_venc_mode *vmode = NULL; @@ -1508,8 +1510,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, writel_relaxed((use_enci ? 1 : 2) | (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) | (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) | - 4 << 5 | - (venc_repeat ? 1 << 8 : 0) | + (ycrcb_map << 5) | + (venc_repeat || yuv420_mode ? 1 << 8 : 0) | (hdmi_repeat ? 1 << 12 : 0), priv->io_base + _REG(VPU_HDMI_SETTING)); diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h index 97eaebbfa0c4..5580bf38e381 100644 --- a/drivers/gpu/drm/meson/meson_venc.h +++ b/drivers/gpu/drm/meson/meson_venc.h @@ -33,6 +33,15 @@ enum { MESON_VENC_MODE_HDMI, }; +enum { + MESON_VENC_MAP_CR_Y_CB = 0, + MESON_VENC_MAP_Y_CB_CR, + MESON_VENC_MAP_Y_CR_CB, + MESON_VENC_MAP_CB_CR_Y, + MESON_VENC_MAP_CB_Y_CR, + MESON_VENC_MAP_CR_CB_Y, +}; + struct meson_cvbs_enci_mode { unsigned int mode_tag; unsigned int hso_begin; /* HSO begin position */ @@ -70,6 +79,8 @@ extern struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc; void meson_venci_cvbs_mode_set(struct meson_drm *priv, struct meson_cvbs_enci_mode *mode); void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, + unsigned int ycrcb_map, + bool yuv420_mode, struct drm_display_mode *mode); unsigned int meson_venci_get_field(struct meson_drm *priv); diff --git a/drivers/gpu/drm/meson/meson_venc_cvbs.c b/drivers/gpu/drm/meson/meson_venc_cvbs.c index 2c5341c881c4..c1bbc601cf13 100644 --- a/drivers/gpu/drm/meson/meson_venc_cvbs.c +++ b/drivers/gpu/drm/meson/meson_venc_cvbs.c @@ -218,7 +218,8 @@ static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder, /* Setup 27MHz vclk2 for ENCI and VDAC */ meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS, MESON_VCLK_CVBS, MESON_VCLK_CVBS, - MESON_VCLK_CVBS, true); + MESON_VCLK_CVBS, MESON_VCLK_CVBS, + true); break; } } -- 2.21.0