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From: John Arbuckle <programmingkidx@gmail.com>
To: richard.henderson@linaro.org, qemu-devel@nongnu.org,
	qemu-ppc@nongnu.orgd, david@gibson.dropbear.id.au,
	mark.cave-ayland@ilande.co.uk
Cc: John Arbuckle <programmingkidx@gmail.com>
Subject: [Qemu-devel] [PATCH 2/2] Implement the PowerPC Floating Point Status and Control Register Fraction Rounded bit
Date: Fri, 24 May 2019 22:20:08 -0400	[thread overview]
Message-ID: <20190525022008.24788-3-programmingkidx@gmail.com> (raw)
In-Reply-To: <20190525022008.24788-1-programmingkidx@gmail.com>

Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
---
 target/ppc/fpu_helper.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 0b7308f539..0baf1ce8e4 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -630,6 +630,10 @@ static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
         env->fpscr &= ~(1 << FPSCR_FI); /* clear the FPSCR[FI] bit */
     }
 
+    /* Set or clear the Fraction Rounded bit */
+    env->fpscr = deposit32(env->fpscr, FPSCR_FR, 1,
+                           (status & float_flag_rounded) != 0);
+
     if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
         (env->error_code & POWERPC_EXCP_FP)) {
         /* Differred floating-point exception after target FPR update */
-- 
2.14.3 (Apple Git-98)



      parent reply	other threads:[~2019-05-25  2:23 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-25  2:20 [Qemu-devel] [PATCH 0/2] Implement PowerPC FPSCR flag Fraction Rounded John Arbuckle
2019-05-25  2:20 ` [Qemu-devel] [PATCH 1/2] Implement Floating Point " John Arbuckle
2019-06-11 21:00   ` Richard Henderson
2019-05-25  2:20 ` John Arbuckle [this message]

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