From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v6 2/2] drm/i915: Make sure we have enough memory bandwidth on ICL
Date: Mon, 27 May 2019 20:55:58 +0300 [thread overview]
Message-ID: <20190527175558.GJ5942@intel.com> (raw)
In-Reply-To: <20190524153614.32410-1-ville.syrjala@linux.intel.com>
On Fri, May 24, 2019 at 06:36:14PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> ICL has so many planes that it can easily exceed the maximum
> effective memory bandwidth of the system. We must therefore check
> that we don't exceed that limit.
>
> The algorithm is very magic number heavy and lacks sufficient
> explanation for now. We also have no sane way to query the
> memory clock and timings, so we must rely on a combination of
> raw readout from the memory controller and hardcoded assumptions.
> The memory controller values obviously change as the system
> jumps between the different SAGV points, so we try to stabilize
> it first by disabling SAGV for the duration of the readout.
>
> The utilized bandwidth is tracked via a device wide atomic
> private object. That is actually not robust because we can't
> afford to enforce strict global ordering between the pipes.
> Thus I think I'll need to change this to simply chop up the
> available bandwidth between all the active pipes. Each pipe
> can then do whatever it wants as long as it doesn't exceed
> its budget. That scheme will also require that we assume that
> any number of planes could be active at any time.
>
> TODO: make it robust and deal with all the open questions
>
> v2: Sleep longer after disabling SAGV
> v3: Poll for the dclk to get raised (seen it take 250ms!)
> If the system has 2133MT/s memory then we pointlessly
> wait one full second :(
> v4: Use the new pcode interface to get the qgv points rather
> that using hardcoded numbers
> v5: Move the pcode stuff into intel_bw.c (Matt)
> s/intel_sagv_info/intel_qgv_info/
> Do the NV12/P010 as per spec for now (Matt)
> s/IS_ICELAKE/IS_GEN11/
> v6: Ignore bandwidth limits if the pcode query fails
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Acked-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Series pushed to dinq. Thanks for the reviews.
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2019-05-27 17:56 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-21 16:40 [PATCH v5 1/2] drm/i915: Make sandybridge_pcode_read() deal with the second data register Ville Syrjala
2019-05-21 16:40 ` [PATCH v5 2/2] drm/i915: Make sure we have enough memory bandwidth on ICL Ville Syrjala
2019-05-24 15:36 ` [PATCH v6 " Ville Syrjala
2019-05-27 17:55 ` Ville Syrjälä [this message]
2019-05-21 18:16 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/2] drm/i915: Make sandybridge_pcode_read() deal with the second data register Patchwork
2019-05-21 18:18 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-05-21 18:37 ` ✓ Fi.CI.BAT: success " Patchwork
2019-05-22 18:28 ` Ville Syrjälä
2019-05-22 13:15 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-05-26 11:25 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/2] drm/i915: Make sandybridge_pcode_read() deal with the second data register (rev2) Patchwork
2019-05-26 11:27 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-05-26 11:42 ` ✓ Fi.CI.BAT: success " Patchwork
2019-05-26 20:09 ` ✓ Fi.CI.IGT: " Patchwork
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