From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] drm/i915/icl: Ensure port A combo PHY HW state is correct
Date: Fri, 31 May 2019 11:26:26 +0300 [thread overview]
Message-ID: <20190531082626.30640-1-imre.deak@intel.com> (raw)
Make sure the HW state of the port A combo PHY is correct wrt. the
IREFGEN setting. This will force a reprogramming during init or a WARN
during uninit if the setting is incorrect.
On my ICL RVP I haven't seen this check failing and leading to a forced
reinit/WARN, but let's add it still for consistency.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_combo_phy.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c b/drivers/gpu/drm/i915/intel_combo_phy.c
index 98213cc58736..841708da5a56 100644
--- a/drivers/gpu/drm/i915/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/intel_combo_phy.c
@@ -198,6 +198,10 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
ret = cnl_verify_procmon_ref_values(dev_priv, port);
+ if (port == PORT_A)
+ ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW8(port),
+ IREFGEN, IREFGEN);
+
ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port),
CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
--
2.17.1
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next reply other threads:[~2019-05-31 8:27 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-31 8:26 Imre Deak [this message]
2019-05-31 12:33 ` [PATCH] drm/i915/icl: Ensure port A combo PHY HW state is correct Ville Syrjälä
2019-05-31 14:40 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-06-01 11:38 ` ✓ Fi.CI.IGT: " Patchwork
2019-06-01 15:20 ` Imre Deak
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