From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Paul E. McKenney" Subject: Re: single copy atomicity for double load/stores on 32-bit systems Date: Mon, 3 Jun 2019 13:13:24 -0700 Message-ID: <20190603201324.GN28207@linux.ibm.com> References: <2fd3a455-6267-5d21-c530-41964a4f6ce9@synopsys.com> <20190531082112.GH2623@hirez.programming.kicks-ass.net> Reply-To: paulmck@linux.ibm.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Vineet Gupta Cc: Peter Zijlstra , Will Deacon , arcml , lkml , "linux-arch@vger.kernel.org" List-Id: linux-arch.vger.kernel.org On Mon, Jun 03, 2019 at 06:08:35PM +0000, Vineet Gupta wrote: > On 5/31/19 1:21 AM, Peter Zijlstra wrote: > >> I'm not sure how to interpret "natural alignment" for the case of double > >> load/stores on 32-bit systems where the hardware and ABI allow for 4 byte > >> alignment (ARCv2 LDD/STD, ARM LDRD/STRD ....) > > Natural alignment: !((uintptr_t)ptr % sizeof(*ptr)) > > > > For any u64 type, that would give 8 byte alignment. the problem > > otherwise being that your data spans two lines/pages etc.. > > Sure, but as Paul said, if the software doesn't expect them to be atomic by > default, they could span 2 hardware lines to keep the implementation simpler/sane. I could imagine 8-byte types being only four-byte aligned on 32-bit systems, but it would be quite a surprise on 64-bit systems. Thanx, Paul From mboxrd@z Thu Jan 1 00:00:00 1970 From: paulmck@linux.ibm.com (Paul E. McKenney) Date: Mon, 3 Jun 2019 13:13:24 -0700 Subject: single copy atomicity for double load/stores on 32-bit systems In-Reply-To: References: <2fd3a455-6267-5d21-c530-41964a4f6ce9@synopsys.com> <20190531082112.GH2623@hirez.programming.kicks-ass.net> List-ID: Message-ID: <20190603201324.GN28207@linux.ibm.com> To: linux-snps-arc@lists.infradead.org On Mon, Jun 03, 2019@06:08:35PM +0000, Vineet Gupta wrote: > On 5/31/19 1:21 AM, Peter Zijlstra wrote: > >> I'm not sure how to interpret "natural alignment" for the case of double > >> load/stores on 32-bit systems where the hardware and ABI allow for 4 byte > >> alignment (ARCv2 LDD/STD, ARM LDRD/STRD ....) > > Natural alignment: !((uintptr_t)ptr % sizeof(*ptr)) > > > > For any u64 type, that would give 8 byte alignment. the problem > > otherwise being that your data spans two lines/pages etc.. > > Sure, but as Paul said, if the software doesn't expect them to be atomic by > default, they could span 2 hardware lines to keep the implementation simpler/sane. I could imagine 8-byte types being only four-byte aligned on 32-bit systems, but it would be quite a surprise on 64-bit systems. Thanx, Paul