From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FEF5C282CE for ; Tue, 4 Jun 2019 16:54:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D427F23CBB for ; Tue, 4 Jun 2019 16:54:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="yaYxGNFK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727985AbfFDQyy (ORCPT ); Tue, 4 Jun 2019 12:54:54 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:55478 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727785AbfFDQyy (ORCPT ); Tue, 4 Jun 2019 12:54:54 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=IHacWH+Djcp8BYpbuXs0K9bY3/ohwLLhjauRh5MYdPA=; b=yaYxGNFKsMUGznjTQV1vU714tU lrJPNhWCV17xJ8y4/sbtYEb/J0aSmqyB9T+xQgEUX8kbIh9uieic5bHLygZCNhyo/LtE62D3KB7jB f7MWfYKaeQzgm9P59Qa261x313LOizoMU0V6U3catLeYw/F4H+KsBFyhuN5XZJW9tX7s=; Received: from andrew by vps0.lunn.ch with local (Exim 4.89) (envelope-from ) id 1hYCi4-0006RX-Oh; Tue, 04 Jun 2019 18:54:52 +0200 Date: Tue, 4 Jun 2019 18:54:52 +0200 From: Andrew Lunn To: Robert Hancock Cc: Heiner Kallweit , netdev@vger.kernel.org, Florian Fainelli Subject: Re: [PATCH net-next v2] net: phy: xilinx: add Xilinx PHY driver Message-ID: <20190604165452.GU19627@lunn.ch> References: <1559603524-18288-1-git-send-email-hancock@sedsystems.ca> <7684776f-2bec-e9e2-1a79-dbc3e9844f7e@sedsystems.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7684776f-2bec-e9e2-1a79-dbc3e9844f7e@sedsystems.ca> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org > So it seems like what is missing is the ability of genphy_config_init to > detect the bits in the extended status register for 1000Base-X and add > the corresponding mode flags. It appears bit 15 for 1000Base-X full > duplex is standardized in 802.3 Clause 22, so I would expect Linux > should be able to detect that and add it as a supported mode for the > PHY. genphy_config_init is dealing with the "legacy" 32-bit mode masks > that have no bit for 1000BaseX though.. how is that intended to work? Hi Robert I think you are looking at an old genphy_config_init(). The u32 has been replaced. Adding: #define ESTATUS_1000_XFULL 0x8000 /* Can do 1000BX Full */ #define ESTATUS_1000_XHALF 0x4000 /* Can do 1000BT Half */ and if (val & ESTATUS_1000_XFULL) linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, features); should not be a problem. Andrew