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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Heinrich Fink <heinrich.fink@daqri.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Fix per-pixel alpha with CCS
Date: Fri, 7 Jun 2019 16:41:34 +0300	[thread overview]
Message-ID: <20190607134134.GY5942@intel.com> (raw)
In-Reply-To: <CAB6MLDZVre9+-3-Nc49-m2fyN_KodvmWo5_sp9V34FDm+93mkw@mail.gmail.com>

On Fri, Jun 07, 2019 at 10:03:17AM +0200, Heinrich Fink wrote:
> On Mon, 3 Jun 2019 at 16:25, Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We forgot to set .has_alpha=true for the A+CCS formats when the code
> > started to consult .has_alpha. This manifests as A+CCS being treated
> > as X+CCS which means no per-pixel alpha blending. Fix the format
> > list appropriately.
> >
> > Cc: stable@vger.kernel.org
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Heinrich Fink <heinrich.fink@daqri.com>
> > Reported-by: Heinrich Fink <heinrich.fink@daqri.com>
> > Fixes: b20815255693 ("drm/i915: Add plane alpha blending support, v2.")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 12 ++++++++----
> >  1 file changed, 8 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index c3e2b1178d55..67d796f4747e 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2463,10 +2463,14 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> >   * main surface.
> >   */
> >  static const struct drm_format_info ccs_formats[] = {
> > -       { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> > -       { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> > -       { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> > -       { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> > +       { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> > +         .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> > +       { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> > +         .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> > +       { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> > +         .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> > +       { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> > +         .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> >  };
> >
> >  static const struct drm_format_info *
> > --
> > 2.21.0
> >
> 
> Just tested it on our image, fixes the bug and works for me. Thank you
> for the swift fix!

Cool. Thanks for confirming the fix.

Pushed to dinq.

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

      reply	other threads:[~2019-06-07 13:41 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-03 14:25 [PATCH] drm/i915: Fix per-pixel alpha with CCS Ville Syrjala
2019-06-03 15:10 ` Maarten Lankhorst
2019-06-03 16:29 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-06-04  4:47 ` ✓ Fi.CI.IGT: " Patchwork
2019-06-07  8:03 ` [PATCH] " Heinrich Fink
2019-06-07 13:41   ` Ville Syrjälä [this message]

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