From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Paul Cercueil <paul@crapouillou.net>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
od@zcrc.me, Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH 1/5] clk: ingenic: Add support for divider tables
Date: Fri, 07 Jun 2019 14:03:45 -0700 [thread overview]
Message-ID: <20190607210346.5EEF8208E3@mail.kernel.org> (raw)
In-Reply-To: <20190502212502.24330-1-paul@crapouillou.net>
Quoting Paul Cercueil (2019-05-02 14:24:58)
> Some clocks provided on Ingenic SoCs have dividers, whose hardware value
> as written in the register cannot be expressed as an affine function
> to the actual divider value.
>
> For instance, for the CPU clock on the JZ4770, the dividers are coded as
> follows:
>
> ------------------
Applied to clk-next
prev parent reply other threads:[~2019-06-07 21:03 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-02 21:24 [PATCH 1/5] clk: ingenic: Add support for divider tables Paul Cercueil
2019-05-02 21:24 ` [PATCH 2/5] clk: ingenic/jz4740: Fix incorrect dividers for main clocks Paul Cercueil
2019-06-07 21:03 ` Stephen Boyd
2019-06-08 10:18 ` Paul Cercueil
2019-05-02 21:25 ` [PATCH 3/5] clk: ingenic/jz4770: " Paul Cercueil
2019-06-07 21:03 ` Stephen Boyd
2019-05-02 21:25 ` [PATCH 4/5] clk: ingenic/jz4725b: " Paul Cercueil
2019-06-07 21:03 ` Stephen Boyd
2019-05-02 21:25 ` [PATCH 5/5] clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly Paul Cercueil
2019-06-07 21:03 ` Stephen Boyd
2019-06-07 21:03 ` Stephen Boyd [this message]
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