From: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
To: qemu-devel@nongnu.org, Laurent Vivier <laurent@vivier.eu>,
Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
Subject: [Qemu-devel] [PATCH v2] The m68k gdbstub SR reg request doesnt include Condition-Codes
Date: Sun, 9 Jun 2019 18:07:13 +0900 [thread overview]
Message-ID: <20190609090713.GA14864@localhost.localdomain> (raw)
The register request via gdbstub would return the SR part
which contains the Trace/Master/IRQ state flags, but
would be missing the CR (Condition Register) state bits.
This fix adds this support by merging them in the m68k
specific gdbstub handler m68k_cpu_gdb_read_register for SR register.
Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
---
Notes:
v1->v2
- remove superfluous braces from my additional code
- slightly amended the commit message
target/m68k/gdbstub.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/m68k/gdbstub.c b/target/m68k/gdbstub.c
index fd2bb46c42..5e5aef5c0f 100644
--- a/target/m68k/gdbstub.c
+++ b/target/m68k/gdbstub.c
@@ -35,8 +35,10 @@ int m68k_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
return gdb_get_reg32(mem_buf, env->aregs[n - 8]);
} else {
switch (n) {
- case 16:
- return gdb_get_reg32(mem_buf, env->sr);
+ case 16: {
+ /* SR is made of SR+CCR, CCR is many 1bit flags so uses helper */
+ return gdb_get_reg32(mem_buf, env->sr | cpu_m68k_get_ccr(env));
+ }
case 17:
return gdb_get_reg32(mem_buf, env->pc);
}
--
2.21.0
next reply other threads:[~2019-06-09 9:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-09 9:07 Lucien Murray-Pitts [this message]
2019-06-09 10:13 ` [Qemu-devel] [PATCH v2] The m68k gdbstub SR reg request doesnt include Condition-Codes Laurent Vivier
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