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[209.51.188.17]) by mx.google.com with ESMTPS id w17si4246487qka.183.2019.06.15.08.44.55 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Jun 2019 08:44:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1]:32878 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcArP-0004KQ-3i for alex.bennee@linaro.org; Sat, 15 Jun 2019 11:44:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35748) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcAqs-0003yI-Uv for qemu-arm@nongnu.org; Sat, 15 Jun 2019 11:44:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hcAqr-0000NI-HV for qemu-arm@nongnu.org; Sat, 15 Jun 2019 11:44:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:48338) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hcAqr-0000KM-8L; Sat, 15 Jun 2019 11:44:21 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 65DF381129; Sat, 15 Jun 2019 15:44:20 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-41.brq.redhat.com [10.40.204.41]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 266831001B05; Sat, 15 Jun 2019 15:44:18 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 15 Jun 2019 17:43:40 +0200 Message-Id: <20190615154352.26824-12-philmd@redhat.com> In-Reply-To: <20190615154352.26824-1-philmd@redhat.com> References: <20190615154352.26824-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Sat, 15 Jun 2019 15:44:20 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-arm] [PATCH v2 11/23] target/arm: Declare v7m_cpacr_pass() publicly X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: rnNj9IUbHfle In the next commit we will move exception handling routines to v7m_helper, so this function will be called from 2 different files. Declare it inlined in the "internals.h" header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 19 ------------------- target/arm/internals.h | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index cf76010ea1..5d05db84d3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7611,25 +7611,6 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uin= t32_t excp_idx, return target_el; } =20 -/* - * Return true if the v7M CPACR permits access to the FPU for the specif= ied - * security state and privilege level. - */ -static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_pri= v) -{ - switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { - case 0: - case 2: /* UNPREDICTABLE: we treat like 0 */ - return false; - case 1: - return is_priv; - case 3: - return true; - default: - g_assert_not_reached(); - } -} - /* * What kind of stack write are we doing? This affects how exceptions * generated during the stacking are treated. diff --git a/target/arm/internals.h b/target/arm/internals.h index 04711b317a..1d15af3f8b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -891,6 +891,27 @@ static inline uint32_t v7m_sp_limit(CPUARMState *env= ) } } =20 +/** + * v7m_cpacr_pass: + * Return true if the v7M CPACR permits access to the FPU for the specif= ied + * security state and privilege level. + */ +static inline bool v7m_cpacr_pass(CPUARMState *env, + bool is_secure, bool is_priv) +{ + switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { + case 0: + case 2: /* UNPREDICTABLE: we treat like 0 */ + return false; + case 1: + return is_priv; + case 3: + return true; + default: + g_assert_not_reached(); + } +} + /** * aarch32_mode_name(): Return name of the AArch32 CPU mode * @psr: Program Status Register indicating CPU mode --=20 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38E3CC31E50 for ; Sat, 15 Jun 2019 15:55:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 110FD21473 for ; Sat, 15 Jun 2019 15:55:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 110FD21473 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:32968 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcB1w-0005st-7D for qemu-devel@archiver.kernel.org; Sat, 15 Jun 2019 11:55:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35801) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcAqw-00041n-QY for qemu-devel@nongnu.org; Sat, 15 Jun 2019 11:44:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hcAqu-0000XS-PD for qemu-devel@nongnu.org; Sat, 15 Jun 2019 11:44:26 -0400 Received: from mx1.redhat.com ([209.132.183.28]:48338) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hcAqr-0000KM-8L; Sat, 15 Jun 2019 11:44:21 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 65DF381129; Sat, 15 Jun 2019 15:44:20 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-41.brq.redhat.com [10.40.204.41]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 266831001B05; Sat, 15 Jun 2019 15:44:18 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 15 Jun 2019 17:43:40 +0200 Message-Id: <20190615154352.26824-12-philmd@redhat.com> In-Reply-To: <20190615154352.26824-1-philmd@redhat.com> References: <20190615154352.26824-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Sat, 15 Jun 2019 15:44:20 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 11/23] target/arm: Declare v7m_cpacr_pass() publicly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" In the next commit we will move exception handling routines to v7m_helper, so this function will be called from 2 different files. Declare it inlined in the "internals.h" header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 19 ------------------- target/arm/internals.h | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index cf76010ea1..5d05db84d3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7611,25 +7611,6 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uin= t32_t excp_idx, return target_el; } =20 -/* - * Return true if the v7M CPACR permits access to the FPU for the specif= ied - * security state and privilege level. - */ -static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_pri= v) -{ - switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { - case 0: - case 2: /* UNPREDICTABLE: we treat like 0 */ - return false; - case 1: - return is_priv; - case 3: - return true; - default: - g_assert_not_reached(); - } -} - /* * What kind of stack write are we doing? This affects how exceptions * generated during the stacking are treated. diff --git a/target/arm/internals.h b/target/arm/internals.h index 04711b317a..1d15af3f8b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -891,6 +891,27 @@ static inline uint32_t v7m_sp_limit(CPUARMState *env= ) } } =20 +/** + * v7m_cpacr_pass: + * Return true if the v7M CPACR permits access to the FPU for the specif= ied + * security state and privilege level. + */ +static inline bool v7m_cpacr_pass(CPUARMState *env, + bool is_secure, bool is_priv) +{ + switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { + case 0: + case 2: /* UNPREDICTABLE: we treat like 0 */ + return false; + case 1: + return is_priv; + case 3: + return true; + default: + g_assert_not_reached(); + } +} + /** * aarch32_mode_name(): Return name of the AArch32 CPU mode * @psr: Program Status Register indicating CPU mode --=20 2.20.1