From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73928C31E5B for ; Tue, 18 Jun 2019 20:25:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3A002206E0 for ; Tue, 18 Jun 2019 20:25:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="c+IQKwFs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730196AbfFRUZJ (ORCPT ); Tue, 18 Jun 2019 16:25:09 -0400 Received: from mail-qt1-f196.google.com ([209.85.160.196]:36802 "EHLO mail-qt1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725909AbfFRUZJ (ORCPT ); Tue, 18 Jun 2019 16:25:09 -0400 Received: by mail-qt1-f196.google.com with SMTP id p15so17110941qtl.3; Tue, 18 Jun 2019 13:25:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MN1rzEtIL+Vh9mjFO+Yd5l/eLtCUYrYg+HZ07MLHDjU=; b=c+IQKwFsS/nOgmRq9p6B8VpXXtMg+4P18crWKkQvl62VW1Z2e/HznvvxJOYN9GU4C2 F2nff19JhV8uEXVCzyZpIPZ64cQ0TjNJYaoFnrqYij+aBZv4oIlyvD8hNmCqKf0SnmEC ZiyfBsuq3wG5KyLpjx56K1tL6VKVfBvBS/0eE/jzpbKVSEwQQSvADcyBjXN0HFK+0UUN //1Hxte9QiEYDGvDwSJwFGZqXqaUVBkASTdIC0Q2L7JQ3e5IWC59vmctCvHGH0JegUY5 tifvqM6pi+fLsIk5arlVA/jGSOhoeCORxATTni3tR5mGRV6k27r3qaEjwjUAzT9bvAmb +lrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MN1rzEtIL+Vh9mjFO+Yd5l/eLtCUYrYg+HZ07MLHDjU=; b=T3AFAC+vobZSMF/HYsl3DVEO54/wDaPhQT01OgtTUbZuDdkxz8UY/W16/AUK1qfJmI P+CAaWXy9tWJ6dS9lZAMRYg3a6cpLDZN/qlzrAs5xc9A1NfxBIkCNTrEZOO/cinknPbS mviwTNqhuqK9mmL+fvFEcGEL07VHtgG1Ry9S1vzvt39AoJqT0EW1xS1Qc8WBE9IpYJcy qA8Xi+4r4pIgoY1yeIUdOiAJF15alt7sYVzqAkx/XY3k/G8OsRPVoJvee9wEHjLAWxt+ NqRvjut0Q4jsFDWfCqesOhcDLMF7Kz6gTRt4xxXIAN1qm+oT2eRjg0K/J0Rwnz7Bs4G6 NiaQ== X-Gm-Message-State: APjAAAWSIrGKqwoC/VV2pgkRBZ7meGP09OloopFWrp+vR+eZKKGTVt12 rqaffavaZmF5rvGIQ9V23YE= X-Google-Smtp-Source: APXvYqwLSzMdfgXL692jrl2/pUxnOxl/2p3+JeCEccFj+7Fsh1psNq3YVQ7tehYPSXpcAiL/TVIhJw== X-Received: by 2002:a0c:b148:: with SMTP id r8mr28741990qvc.240.1560889508131; Tue, 18 Jun 2019 13:25:08 -0700 (PDT) Received: from localhost ([2601:184:4780:7861:5010:5849:d76d:b714]) by smtp.gmail.com with ESMTPSA id i1sm302977qtb.7.2019.06.18.13.25.07 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 18 Jun 2019 13:25:07 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, Sean Paul , Georgi Djakov , Jayant Shekhar , Sravanthi Kollukuduru , Rob Clark , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jeykumar Sankaran , Jordan Crouse , Bruce Wang , Abhinav Kumar , freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] drm/msm/dpu: clean up references of DPU custom bus scaling Date: Tue, 18 Jun 2019 13:24:09 -0700 Message-Id: <20190618202425.15259-2-robdclark@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190618202425.15259-1-robdclark@gmail.com> References: <20190618202425.15259-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jayant Shekhar Since the upstream interconnect bus framework has landed upstream, the existing references of custom bus scaling needs to be cleaned up. Changes in v2: - Fixed build error due to partial clean up Changes in v3: - Condense multiple lines into a single line (Sean Paul) Changes in v4-v7: - None Signed-off-by: Sravanthi Kollukuduru Signed-off-by: Jayant Shekhar Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 174 +++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 +- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 22 +-- 4 files changed, 80 insertions(+), 131 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 9f20f397f77d..e231c37a9dbb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -77,7 +77,6 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, struct dpu_core_perf_params *perf) { struct dpu_crtc_state *dpu_cstate; - int i; if (!kms || !kms->catalog || !crtc || !state || !perf) { DPU_ERROR("invalid parameters\n"); @@ -88,35 +87,24 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, memset(perf, 0, sizeof(struct dpu_core_perf_params)); if (!dpu_cstate->bw_control) { - for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { - perf->bw_ctl[i] = kms->catalog->perf.max_bw_high * + perf->bw_ctl = kms->catalog->perf.max_bw_high * 1000ULL; - perf->max_per_pipe_ib[i] = perf->bw_ctl[i]; - } + perf->max_per_pipe_ib = perf->bw_ctl; perf->core_clk_rate = kms->perf.max_core_clk_rate; } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) { - for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { - perf->bw_ctl[i] = 0; - perf->max_per_pipe_ib[i] = 0; - } + perf->bw_ctl = 0; + perf->max_per_pipe_ib = 0; perf->core_clk_rate = 0; } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) { - for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { - perf->bw_ctl[i] = kms->perf.fix_core_ab_vote; - perf->max_per_pipe_ib[i] = kms->perf.fix_core_ib_vote; - } + perf->bw_ctl = kms->perf.fix_core_ab_vote; + perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote; perf->core_clk_rate = kms->perf.fix_core_clk_rate; } DPU_DEBUG( - "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu llcc_ib=%llu llcc_ab=%llu mem_ib=%llu mem_ab=%llu\n", + "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n", crtc->base.id, perf->core_clk_rate, - perf->max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_MNOC], - perf->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MNOC], - perf->max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_LLCC], - perf->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_LLCC], - perf->max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_EBI], - perf->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_EBI]); + perf->max_per_pipe_ib, perf->bw_ctl); } int dpu_core_perf_crtc_check(struct drm_crtc *crtc, @@ -129,7 +117,6 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, struct dpu_crtc_state *dpu_cstate; struct drm_crtc *tmp_crtc; struct dpu_kms *kms; - int i; if (!crtc || !state) { DPU_ERROR("invalid crtc\n"); @@ -151,31 +138,25 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, /* obtain new values */ _dpu_core_perf_calc_crtc(kms, crtc, state, &dpu_cstate->new_perf); - for (i = DPU_CORE_PERF_DATA_BUS_ID_MNOC; - i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { - bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl[i]; - curr_client_type = dpu_crtc_get_client_type(crtc); + bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl; + curr_client_type = dpu_crtc_get_client_type(crtc); - drm_for_each_crtc(tmp_crtc, crtc->dev) { - if (tmp_crtc->enabled && - (dpu_crtc_get_client_type(tmp_crtc) == - curr_client_type) && - (tmp_crtc != crtc)) { - struct dpu_crtc_state *tmp_cstate = - to_dpu_crtc_state(tmp_crtc->state); - - DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n", - tmp_crtc->base.id, - tmp_cstate->new_perf.bw_ctl[i], - tmp_cstate->bw_control); - /* - * For bw check only use the bw if the - * atomic property has been already set - */ - if (tmp_cstate->bw_control) - bw_sum_of_intfs += - tmp_cstate->new_perf.bw_ctl[i]; - } + drm_for_each_crtc(tmp_crtc, crtc->dev) { + if (tmp_crtc->enabled && + (dpu_crtc_get_client_type(tmp_crtc) == + curr_client_type) && (tmp_crtc != crtc)) { + struct dpu_crtc_state *tmp_cstate = + to_dpu_crtc_state(tmp_crtc->state); + + DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n", + tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl, + tmp_cstate->bw_control); + /* + * For bw check only use the bw if the + * atomic property has been already set + */ + if (tmp_cstate->bw_control) + bw_sum_of_intfs += tmp_cstate->new_perf.bw_ctl; } /* convert bandwidth to kb */ @@ -206,9 +187,9 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, } static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, - struct drm_crtc *crtc, u32 bus_id) + struct drm_crtc *crtc) { - struct dpu_core_perf_params perf = { { 0 } }; + struct dpu_core_perf_params perf = { 0 }; enum dpu_crtc_client_type curr_client_type = dpu_crtc_get_client_type(crtc); struct drm_crtc *tmp_crtc; @@ -221,13 +202,11 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, dpu_crtc_get_client_type(tmp_crtc)) { dpu_cstate = to_dpu_crtc_state(tmp_crtc->state); - perf.max_per_pipe_ib[bus_id] = - max(perf.max_per_pipe_ib[bus_id], - dpu_cstate->new_perf.max_per_pipe_ib[bus_id]); + perf.max_per_pipe_ib = max(perf.max_per_pipe_ib, + dpu_cstate->new_perf.max_per_pipe_ib); - DPU_DEBUG("crtc=%d bus_id=%d bw=%llu\n", - tmp_crtc->base.id, bus_id, - dpu_cstate->new_perf.bw_ctl[bus_id]); + DPU_DEBUG("crtc=%d bw=%llu\n", tmp_crtc->base.id, + dpu_cstate->new_perf.bw_ctl); } } return ret; @@ -247,7 +226,6 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) struct dpu_crtc *dpu_crtc; struct dpu_crtc_state *dpu_cstate; struct dpu_kms *kms; - int i; if (!crtc) { DPU_ERROR("invalid crtc\n"); @@ -283,10 +261,8 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) if (kms->perf.enable_bw_release) { trace_dpu_cmd_release_bw(crtc->base.id); DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id); - for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { - dpu_crtc->cur_perf.bw_ctl[i] = 0; - _dpu_core_perf_crtc_update_bus(kms, crtc, i); - } + dpu_crtc->cur_perf.bw_ctl = 0; + _dpu_core_perf_crtc_update_bus(kms, crtc); } } @@ -329,11 +305,10 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, int params_changed, bool stop_req) { struct dpu_core_perf_params *new, *old; - int update_bus = 0, update_clk = 0; + bool update_bus = false, update_clk = false; u64 clk_rate = 0; struct dpu_crtc *dpu_crtc; struct dpu_crtc_state *dpu_cstate; - int i; struct msm_drm_private *priv; struct dpu_kms *kms; int ret; @@ -360,62 +335,49 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, new = &dpu_cstate->new_perf; if (crtc->enabled && !stop_req) { - for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { - /* - * cases for bus bandwidth update. - * 1. new bandwidth vote - "ab or ib vote" is higher - * than current vote for update request. - * 2. new bandwidth vote - "ab or ib vote" is lower - * than current vote at end of commit or stop. - */ - if ((params_changed && ((new->bw_ctl[i] > - old->bw_ctl[i]) || - (new->max_per_pipe_ib[i] > - old->max_per_pipe_ib[i]))) || - (!params_changed && ((new->bw_ctl[i] < - old->bw_ctl[i]) || - (new->max_per_pipe_ib[i] < - old->max_per_pipe_ib[i])))) { - DPU_DEBUG( - "crtc=%d p=%d new_bw=%llu,old_bw=%llu\n", - crtc->base.id, params_changed, - new->bw_ctl[i], old->bw_ctl[i]); - old->bw_ctl[i] = new->bw_ctl[i]; - old->max_per_pipe_ib[i] = - new->max_per_pipe_ib[i]; - update_bus |= BIT(i); - } + /* + * cases for bus bandwidth update. + * 1. new bandwidth vote - "ab or ib vote" is higher + * than current vote for update request. + * 2. new bandwidth vote - "ab or ib vote" is lower + * than current vote at end of commit or stop. + */ + if ((params_changed && ((new->bw_ctl > old->bw_ctl) || + (new->max_per_pipe_ib > old->max_per_pipe_ib))) || + (!params_changed && ((new->bw_ctl < old->bw_ctl) || + (new->max_per_pipe_ib < old->max_per_pipe_ib)))) { + DPU_DEBUG("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n", + crtc->base.id, params_changed, + new->bw_ctl, old->bw_ctl); + old->bw_ctl = new->bw_ctl; + old->max_per_pipe_ib = new->max_per_pipe_ib; + update_bus = true; } if ((params_changed && - (new->core_clk_rate > old->core_clk_rate)) || - (!params_changed && - (new->core_clk_rate < old->core_clk_rate))) { + (new->core_clk_rate > old->core_clk_rate)) || + (!params_changed && + (new->core_clk_rate < old->core_clk_rate))) { old->core_clk_rate = new->core_clk_rate; - update_clk = 1; + update_clk = true; } } else { DPU_DEBUG("crtc=%d disable\n", crtc->base.id); memset(old, 0, sizeof(*old)); memset(new, 0, sizeof(*new)); - update_bus = ~0; - update_clk = 1; + update_bus = true; + update_clk = true; } - trace_dpu_perf_crtc_update(crtc->base.id, - new->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MNOC], - new->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_LLCC], - new->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_EBI], - new->core_clk_rate, stop_req, - update_bus, update_clk); - - for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { - if (update_bus & BIT(i)) { - ret = _dpu_core_perf_crtc_update_bus(kms, crtc, i); - if (ret) { - DPU_ERROR("crtc-%d: failed to update bw vote for bus-%d\n", - crtc->base.id, i); - return ret; - } + + trace_dpu_perf_crtc_update(crtc->base.id, new->bw_ctl, + new->core_clk_rate, stop_req, update_bus, update_clk); + + if (update_bus) { + ret = _dpu_core_perf_crtc_update_bus(kms, crtc); + if (ret) { + DPU_ERROR("crtc-%d: failed to update bus bw vote\n", + crtc->base.id); + return ret; } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h index 37f518815eb7..d2097ef3d716 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h @@ -42,8 +42,8 @@ enum dpu_core_perf_data_bus_id { * @core_clk_rate: core clock rate request */ struct dpu_core_perf_params { - u64 max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_MAX]; - u64 bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MAX]; + u64 max_per_pipe_ib; + u64 bw_ctl; u64 core_clk_rate; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index dfdfa766da8f..c4db60a8672d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1235,19 +1235,14 @@ static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v) { struct drm_crtc *crtc = (struct drm_crtc *) s->private; struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); - int i; seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc)); seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc)); seq_printf(s, "core_clk_rate: %llu\n", dpu_crtc->cur_perf.core_clk_rate); - for (i = DPU_CORE_PERF_DATA_BUS_ID_MNOC; - i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { - seq_printf(s, "bw_ctl[%d]: %llu\n", i, - dpu_crtc->cur_perf.bw_ctl[i]); - seq_printf(s, "max_per_pipe_ib[%d]: %llu\n", i, - dpu_crtc->cur_perf.max_per_pipe_ib[i]); - } + seq_printf(s, "bw_ctl: %llu\n", dpu_crtc->cur_perf.bw_ctl); + seq_printf(s, "max_per_pipe_ib: %llu\n", + dpu_crtc->cur_perf.max_per_pipe_ib); return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 8bb46090bd16..1d68e214795e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -146,16 +146,12 @@ TRACE_EVENT(dpu_trace_counter, ) TRACE_EVENT(dpu_perf_crtc_update, - TP_PROTO(u32 crtc, u64 bw_ctl_mnoc, u64 bw_ctl_llcc, - u64 bw_ctl_ebi, u32 core_clk_rate, - bool stop_req, u32 update_bus, u32 update_clk), - TP_ARGS(crtc, bw_ctl_mnoc, bw_ctl_llcc, bw_ctl_ebi, core_clk_rate, - stop_req, update_bus, update_clk), + TP_PROTO(u32 crtc, u64 bw_ctl, u32 core_clk_rate, + bool stop_req, bool update_bus, bool update_clk), + TP_ARGS(crtc, bw_ctl, core_clk_rate, stop_req, update_bus, update_clk), TP_STRUCT__entry( __field(u32, crtc) - __field(u64, bw_ctl_mnoc) - __field(u64, bw_ctl_llcc) - __field(u64, bw_ctl_ebi) + __field(u64, bw_ctl) __field(u32, core_clk_rate) __field(bool, stop_req) __field(u32, update_bus) @@ -163,20 +159,16 @@ TRACE_EVENT(dpu_perf_crtc_update, ), TP_fast_assign( __entry->crtc = crtc; - __entry->bw_ctl_mnoc = bw_ctl_mnoc; - __entry->bw_ctl_llcc = bw_ctl_llcc; - __entry->bw_ctl_ebi = bw_ctl_ebi; + __entry->bw_ctl = bw_ctl; __entry->core_clk_rate = core_clk_rate; __entry->stop_req = stop_req; __entry->update_bus = update_bus; __entry->update_clk = update_clk; ), TP_printk( - "crtc=%d bw_mnoc=%llu bw_llcc=%llu bw_ebi=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d", + "crtc=%d bw_ctl=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d", __entry->crtc, - __entry->bw_ctl_mnoc, - __entry->bw_ctl_llcc, - __entry->bw_ctl_ebi, + __entry->bw_ctl, __entry->core_clk_rate, __entry->stop_req, __entry->update_bus, -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Clark Subject: [PATCH 1/5] drm/msm/dpu: clean up references of DPU custom bus scaling Date: Tue, 18 Jun 2019 13:24:09 -0700 Message-ID: <20190618202425.15259-2-robdclark@gmail.com> References: <20190618202425.15259-1-robdclark@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20190618202425.15259-1-robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Rob Clark , Bruce Wang , David Airlie , linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Jordan Crouse , Abhinav Kumar , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Jayant Shekhar , Rob Clark , Sean Paul , Daniel Vetter , Jeykumar Sankaran , freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, Sean Paul , Georgi Djakov , Sravanthi Kollukuduru List-Id: dri-devel@lists.freedesktop.org RnJvbTogSmF5YW50IFNoZWtoYXIgPGpzaGVraGFyQGNvZGVhdXJvcmEub3JnPgoKU2luY2UgdGhl IHVwc3RyZWFtIGludGVyY29ubmVjdCBidXMgZnJhbWV3b3JrIGhhcyBsYW5kZWQKdXBzdHJlYW0s IHRoZSBleGlzdGluZyByZWZlcmVuY2VzIG9mIGN1c3RvbSBidXMgc2NhbGluZwpuZWVkcyB0byBi ZSBjbGVhbmVkIHVwLgoKQ2hhbmdlcyBpbiB2MjoKCS0gRml4ZWQgYnVpbGQgZXJyb3IgZHVlIHRv IHBhcnRpYWwgY2xlYW4gdXAKCkNoYW5nZXMgaW4gdjM6CgktIENvbmRlbnNlIG11bHRpcGxlIGxp bmVzIGludG8gYSBzaW5nbGUgbGluZSAoU2VhbiBQYXVsKQoKQ2hhbmdlcyBpbiB2NC12NzoKCS0g Tm9uZQoKU2lnbmVkLW9mZi1ieTogU3JhdmFudGhpIEtvbGx1a3VkdXJ1IDxza29sbHVrdUBjb2Rl YXVyb3JhLm9yZz4KU2lnbmVkLW9mZi1ieTogSmF5YW50IFNoZWtoYXIgPGpzaGVraGFyQGNvZGVh dXJvcmEub3JnPgpTaWduZWQtb2ZmLWJ5OiBSb2IgQ2xhcmsgPHJvYmRjbGFya0BjaHJvbWl1bS5v cmc+Ci0tLQogZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1X2NvcmVfcGVyZi5jIHwg MTc0ICsrKysrKystLS0tLS0tLS0tLQogZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1 X2NvcmVfcGVyZi5oIHwgICA0ICstCiBkcml2ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvZHB1MS9kcHVf Y3J0Yy5jICAgICAgfCAgMTEgKy0KIGRyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV90 cmFjZS5oICAgICB8ICAyMiArLS0KIDQgZmlsZXMgY2hhbmdlZCwgODAgaW5zZXJ0aW9ucygrKSwg MTMxIGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9k cHUxL2RwdV9jb3JlX3BlcmYuYyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9j b3JlX3BlcmYuYwppbmRleCA5ZjIwZjM5N2Y3N2QuLmUyMzFjMzdhOWRiYiAxMDA2NDQKLS0tIGEv ZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1X2NvcmVfcGVyZi5jCisrKyBiL2RyaXZl cnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9jb3JlX3BlcmYuYwpAQCAtNzcsNyArNzcsNiBA QCBzdGF0aWMgdm9pZCBfZHB1X2NvcmVfcGVyZl9jYWxjX2NydGMoc3RydWN0IGRwdV9rbXMgKmtt cywKIAkJc3RydWN0IGRwdV9jb3JlX3BlcmZfcGFyYW1zICpwZXJmKQogewogCXN0cnVjdCBkcHVf Y3J0Y19zdGF0ZSAqZHB1X2NzdGF0ZTsKLQlpbnQgaTsKIAogCWlmICgha21zIHx8ICFrbXMtPmNh dGFsb2cgfHwgIWNydGMgfHwgIXN0YXRlIHx8ICFwZXJmKSB7CiAJCURQVV9FUlJPUigiaW52YWxp ZCBwYXJhbWV0ZXJzXG4iKTsKQEAgLTg4LDM1ICs4NywyNCBAQCBzdGF0aWMgdm9pZCBfZHB1X2Nv cmVfcGVyZl9jYWxjX2NydGMoc3RydWN0IGRwdV9rbXMgKmttcywKIAltZW1zZXQocGVyZiwgMCwg c2l6ZW9mKHN0cnVjdCBkcHVfY29yZV9wZXJmX3BhcmFtcykpOwogCiAJaWYgKCFkcHVfY3N0YXRl LT5id19jb250cm9sKSB7Ci0JCWZvciAoaSA9IDA7IGkgPCBEUFVfQ09SRV9QRVJGX0RBVEFfQlVT X0lEX01BWDsgaSsrKSB7Ci0JCQlwZXJmLT5id19jdGxbaV0gPSBrbXMtPmNhdGFsb2ctPnBlcmYu bWF4X2J3X2hpZ2ggKgorCQlwZXJmLT5id19jdGwgPSBrbXMtPmNhdGFsb2ctPnBlcmYubWF4X2J3 X2hpZ2ggKgogCQkJCQkxMDAwVUxMOwotCQkJcGVyZi0+bWF4X3Blcl9waXBlX2liW2ldID0gcGVy Zi0+YndfY3RsW2ldOwotCQl9CisJCXBlcmYtPm1heF9wZXJfcGlwZV9pYiA9IHBlcmYtPmJ3X2N0 bDsKIAkJcGVyZi0+Y29yZV9jbGtfcmF0ZSA9IGttcy0+cGVyZi5tYXhfY29yZV9jbGtfcmF0ZTsK IAl9IGVsc2UgaWYgKGttcy0+cGVyZi5wZXJmX3R1bmUubW9kZSA9PSBEUFVfUEVSRl9NT0RFX01J TklNVU0pIHsKLQkJZm9yIChpID0gMDsgaSA8IERQVV9DT1JFX1BFUkZfREFUQV9CVVNfSURfTUFY OyBpKyspIHsKLQkJCXBlcmYtPmJ3X2N0bFtpXSA9IDA7Ci0JCQlwZXJmLT5tYXhfcGVyX3BpcGVf aWJbaV0gPSAwOwotCQl9CisJCXBlcmYtPmJ3X2N0bCA9IDA7CisJCXBlcmYtPm1heF9wZXJfcGlw ZV9pYiA9IDA7CiAJCXBlcmYtPmNvcmVfY2xrX3JhdGUgPSAwOwogCX0gZWxzZSBpZiAoa21zLT5w ZXJmLnBlcmZfdHVuZS5tb2RlID09IERQVV9QRVJGX01PREVfRklYRUQpIHsKLQkJZm9yIChpID0g MDsgaSA8IERQVV9DT1JFX1BFUkZfREFUQV9CVVNfSURfTUFYOyBpKyspIHsKLQkJCXBlcmYtPmJ3 X2N0bFtpXSA9IGttcy0+cGVyZi5maXhfY29yZV9hYl92b3RlOwotCQkJcGVyZi0+bWF4X3Blcl9w aXBlX2liW2ldID0ga21zLT5wZXJmLmZpeF9jb3JlX2liX3ZvdGU7Ci0JCX0KKwkJcGVyZi0+Yndf Y3RsID0ga21zLT5wZXJmLmZpeF9jb3JlX2FiX3ZvdGU7CisJCXBlcmYtPm1heF9wZXJfcGlwZV9p YiA9IGttcy0+cGVyZi5maXhfY29yZV9pYl92b3RlOwogCQlwZXJmLT5jb3JlX2Nsa19yYXRlID0g a21zLT5wZXJmLmZpeF9jb3JlX2Nsa19yYXRlOwogCX0KIAogCURQVV9ERUJVRygKLQkJImNydGM9 JWQgY2xrX3JhdGU9JWxsdSBjb3JlX2liPSVsbHUgY29yZV9hYj0lbGx1IGxsY2NfaWI9JWxsdSBs bGNjX2FiPSVsbHUgbWVtX2liPSVsbHUgbWVtX2FiPSVsbHVcbiIsCisJCSJjcnRjPSVkIGNsa19y YXRlPSVsbHUgY29yZV9pYj0lbGx1IGNvcmVfYWI9JWxsdVxuIiwKIAkJCWNydGMtPmJhc2UuaWQs IHBlcmYtPmNvcmVfY2xrX3JhdGUsCi0JCQlwZXJmLT5tYXhfcGVyX3BpcGVfaWJbRFBVX0NPUkVf UEVSRl9EQVRBX0JVU19JRF9NTk9DXSwKLQkJCXBlcmYtPmJ3X2N0bFtEUFVfQ09SRV9QRVJGX0RB VEFfQlVTX0lEX01OT0NdLAotCQkJcGVyZi0+bWF4X3Blcl9waXBlX2liW0RQVV9DT1JFX1BFUkZf REFUQV9CVVNfSURfTExDQ10sCi0JCQlwZXJmLT5id19jdGxbRFBVX0NPUkVfUEVSRl9EQVRBX0JV U19JRF9MTENDXSwKLQkJCXBlcmYtPm1heF9wZXJfcGlwZV9pYltEUFVfQ09SRV9QRVJGX0RBVEFf QlVTX0lEX0VCSV0sCi0JCQlwZXJmLT5id19jdGxbRFBVX0NPUkVfUEVSRl9EQVRBX0JVU19JRF9F QkldKTsKKwkJCXBlcmYtPm1heF9wZXJfcGlwZV9pYiwgcGVyZi0+YndfY3RsKTsKIH0KIAogaW50 IGRwdV9jb3JlX3BlcmZfY3J0Y19jaGVjayhzdHJ1Y3QgZHJtX2NydGMgKmNydGMsCkBAIC0xMjks NyArMTE3LDYgQEAgaW50IGRwdV9jb3JlX3BlcmZfY3J0Y19jaGVjayhzdHJ1Y3QgZHJtX2NydGMg KmNydGMsCiAJc3RydWN0IGRwdV9jcnRjX3N0YXRlICpkcHVfY3N0YXRlOwogCXN0cnVjdCBkcm1f Y3J0YyAqdG1wX2NydGM7CiAJc3RydWN0IGRwdV9rbXMgKmttczsKLQlpbnQgaTsKIAogCWlmICgh Y3J0YyB8fCAhc3RhdGUpIHsKIAkJRFBVX0VSUk9SKCJpbnZhbGlkIGNydGNcbiIpOwpAQCAtMTUx LDMxICsxMzgsMjUgQEAgaW50IGRwdV9jb3JlX3BlcmZfY3J0Y19jaGVjayhzdHJ1Y3QgZHJtX2Ny dGMgKmNydGMsCiAJLyogb2J0YWluIG5ldyB2YWx1ZXMgKi8KIAlfZHB1X2NvcmVfcGVyZl9jYWxj X2NydGMoa21zLCBjcnRjLCBzdGF0ZSwgJmRwdV9jc3RhdGUtPm5ld19wZXJmKTsKIAotCWZvciAo aSA9IERQVV9DT1JFX1BFUkZfREFUQV9CVVNfSURfTU5PQzsKLQkJCWkgPCBEUFVfQ09SRV9QRVJG X0RBVEFfQlVTX0lEX01BWDsgaSsrKSB7Ci0JCWJ3X3N1bV9vZl9pbnRmcyA9IGRwdV9jc3RhdGUt Pm5ld19wZXJmLmJ3X2N0bFtpXTsKLQkJY3Vycl9jbGllbnRfdHlwZSA9IGRwdV9jcnRjX2dldF9j bGllbnRfdHlwZShjcnRjKTsKKwlid19zdW1fb2ZfaW50ZnMgPSBkcHVfY3N0YXRlLT5uZXdfcGVy Zi5id19jdGw7CisJY3Vycl9jbGllbnRfdHlwZSA9IGRwdV9jcnRjX2dldF9jbGllbnRfdHlwZShj cnRjKTsKIAotCQlkcm1fZm9yX2VhY2hfY3J0Yyh0bXBfY3J0YywgY3J0Yy0+ZGV2KSB7Ci0JCQlp ZiAodG1wX2NydGMtPmVuYWJsZWQgJiYKLQkJCSAgICAoZHB1X2NydGNfZ2V0X2NsaWVudF90eXBl KHRtcF9jcnRjKSA9PQotCQkJCQkgICAgY3Vycl9jbGllbnRfdHlwZSkgJiYKLQkJCSAgICAodG1w X2NydGMgIT0gY3J0YykpIHsKLQkJCQlzdHJ1Y3QgZHB1X2NydGNfc3RhdGUgKnRtcF9jc3RhdGUg PQotCQkJCQl0b19kcHVfY3J0Y19zdGF0ZSh0bXBfY3J0Yy0+c3RhdGUpOwotCi0JCQkJRFBVX0RF QlVHKCJjcnRjOiVkIGJ3OiVsbHUgY3RybDolZFxuIiwKLQkJCQkJdG1wX2NydGMtPmJhc2UuaWQs Ci0JCQkJCXRtcF9jc3RhdGUtPm5ld19wZXJmLmJ3X2N0bFtpXSwKLQkJCQkJdG1wX2NzdGF0ZS0+ YndfY29udHJvbCk7Ci0JCQkJLyoKLQkJCQkgKiBGb3IgYncgY2hlY2sgb25seSB1c2UgdGhlIGJ3 IGlmIHRoZQotCQkJCSAqIGF0b21pYyBwcm9wZXJ0eSBoYXMgYmVlbiBhbHJlYWR5IHNldAotCQkJ CSAqLwotCQkJCWlmICh0bXBfY3N0YXRlLT5id19jb250cm9sKQotCQkJCQlid19zdW1fb2ZfaW50 ZnMgKz0KLQkJCQkJCXRtcF9jc3RhdGUtPm5ld19wZXJmLmJ3X2N0bFtpXTsKLQkJCX0KKwlkcm1f Zm9yX2VhY2hfY3J0Yyh0bXBfY3J0YywgY3J0Yy0+ZGV2KSB7CisJCWlmICh0bXBfY3J0Yy0+ZW5h YmxlZCAmJgorCQkgICAgKGRwdV9jcnRjX2dldF9jbGllbnRfdHlwZSh0bXBfY3J0YykgPT0KKwkJ CQljdXJyX2NsaWVudF90eXBlKSAmJiAodG1wX2NydGMgIT0gY3J0YykpIHsKKwkJCXN0cnVjdCBk cHVfY3J0Y19zdGF0ZSAqdG1wX2NzdGF0ZSA9CisJCQkJdG9fZHB1X2NydGNfc3RhdGUodG1wX2Ny dGMtPnN0YXRlKTsKKworCQkJRFBVX0RFQlVHKCJjcnRjOiVkIGJ3OiVsbHUgY3RybDolZFxuIiwK KwkJCQl0bXBfY3J0Yy0+YmFzZS5pZCwgdG1wX2NzdGF0ZS0+bmV3X3BlcmYuYndfY3RsLAorCQkJ CXRtcF9jc3RhdGUtPmJ3X2NvbnRyb2wpOworCQkJLyoKKwkJCSAqIEZvciBidyBjaGVjayBvbmx5 IHVzZSB0aGUgYncgaWYgdGhlCisJCQkgKiBhdG9taWMgcHJvcGVydHkgaGFzIGJlZW4gYWxyZWFk eSBzZXQKKwkJCSAqLworCQkJaWYgKHRtcF9jc3RhdGUtPmJ3X2NvbnRyb2wpCisJCQkJYndfc3Vt X29mX2ludGZzICs9IHRtcF9jc3RhdGUtPm5ld19wZXJmLmJ3X2N0bDsKIAkJfQogCiAJCS8qIGNv bnZlcnQgYmFuZHdpZHRoIHRvIGtiICovCkBAIC0yMDYsOSArMTg3LDkgQEAgaW50IGRwdV9jb3Jl X3BlcmZfY3J0Y19jaGVjayhzdHJ1Y3QgZHJtX2NydGMgKmNydGMsCiB9CiAKIHN0YXRpYyBpbnQg X2RwdV9jb3JlX3BlcmZfY3J0Y191cGRhdGVfYnVzKHN0cnVjdCBkcHVfa21zICprbXMsCi0JCXN0 cnVjdCBkcm1fY3J0YyAqY3J0YywgdTMyIGJ1c19pZCkKKwkJc3RydWN0IGRybV9jcnRjICpjcnRj KQogewotCXN0cnVjdCBkcHVfY29yZV9wZXJmX3BhcmFtcyBwZXJmID0geyB7IDAgfSB9OworCXN0 cnVjdCBkcHVfY29yZV9wZXJmX3BhcmFtcyBwZXJmID0geyAwIH07CiAJZW51bSBkcHVfY3J0Y19j bGllbnRfdHlwZSBjdXJyX2NsaWVudF90eXBlCiAJCQkJCT0gZHB1X2NydGNfZ2V0X2NsaWVudF90 eXBlKGNydGMpOwogCXN0cnVjdCBkcm1fY3J0YyAqdG1wX2NydGM7CkBAIC0yMjEsMTMgKzIwMiwx MSBAQCBzdGF0aWMgaW50IF9kcHVfY29yZV9wZXJmX2NydGNfdXBkYXRlX2J1cyhzdHJ1Y3QgZHB1 X2ttcyAqa21zLAogCQkJCWRwdV9jcnRjX2dldF9jbGllbnRfdHlwZSh0bXBfY3J0YykpIHsKIAkJ CWRwdV9jc3RhdGUgPSB0b19kcHVfY3J0Y19zdGF0ZSh0bXBfY3J0Yy0+c3RhdGUpOwogCi0JCQlw ZXJmLm1heF9wZXJfcGlwZV9pYltidXNfaWRdID0KLQkJCQltYXgocGVyZi5tYXhfcGVyX3BpcGVf aWJbYnVzX2lkXSwKLQkJCQlkcHVfY3N0YXRlLT5uZXdfcGVyZi5tYXhfcGVyX3BpcGVfaWJbYnVz X2lkXSk7CisJCQlwZXJmLm1heF9wZXJfcGlwZV9pYiA9IG1heChwZXJmLm1heF9wZXJfcGlwZV9p YiwKKwkJCQkJZHB1X2NzdGF0ZS0+bmV3X3BlcmYubWF4X3Blcl9waXBlX2liKTsKIAotCQkJRFBV X0RFQlVHKCJjcnRjPSVkIGJ1c19pZD0lZCBidz0lbGx1XG4iLAotCQkJCXRtcF9jcnRjLT5iYXNl LmlkLCBidXNfaWQsCi0JCQkJZHB1X2NzdGF0ZS0+bmV3X3BlcmYuYndfY3RsW2J1c19pZF0pOwor CQkJRFBVX0RFQlVHKCJjcnRjPSVkIGJ3PSVsbHVcbiIsIHRtcF9jcnRjLT5iYXNlLmlkLAorCQkJ CQlkcHVfY3N0YXRlLT5uZXdfcGVyZi5id19jdGwpOwogCQl9CiAJfQogCXJldHVybiByZXQ7CkBA IC0yNDcsNyArMjI2LDYgQEAgdm9pZCBkcHVfY29yZV9wZXJmX2NydGNfcmVsZWFzZV9idyhzdHJ1 Y3QgZHJtX2NydGMgKmNydGMpCiAJc3RydWN0IGRwdV9jcnRjICpkcHVfY3J0YzsKIAlzdHJ1Y3Qg ZHB1X2NydGNfc3RhdGUgKmRwdV9jc3RhdGU7CiAJc3RydWN0IGRwdV9rbXMgKmttczsKLQlpbnQg aTsKIAogCWlmICghY3J0YykgewogCQlEUFVfRVJST1IoImludmFsaWQgY3J0Y1xuIik7CkBAIC0y ODMsMTAgKzI2MSw4IEBAIHZvaWQgZHB1X2NvcmVfcGVyZl9jcnRjX3JlbGVhc2VfYncoc3RydWN0 IGRybV9jcnRjICpjcnRjKQogCWlmIChrbXMtPnBlcmYuZW5hYmxlX2J3X3JlbGVhc2UpIHsKIAkJ dHJhY2VfZHB1X2NtZF9yZWxlYXNlX2J3KGNydGMtPmJhc2UuaWQpOwogCQlEUFVfREVCVUcoIlJl bGVhc2UgQlcgY3J0Yz0lZFxuIiwgY3J0Yy0+YmFzZS5pZCk7Ci0JCWZvciAoaSA9IDA7IGkgPCBE UFVfQ09SRV9QRVJGX0RBVEFfQlVTX0lEX01BWDsgaSsrKSB7Ci0JCQlkcHVfY3J0Yy0+Y3VyX3Bl cmYuYndfY3RsW2ldID0gMDsKLQkJCV9kcHVfY29yZV9wZXJmX2NydGNfdXBkYXRlX2J1cyhrbXMs IGNydGMsIGkpOwotCQl9CisJCWRwdV9jcnRjLT5jdXJfcGVyZi5id19jdGwgPSAwOworCQlfZHB1 X2NvcmVfcGVyZl9jcnRjX3VwZGF0ZV9idXMoa21zLCBjcnRjKTsKIAl9CiB9CiAKQEAgLTMyOSwx MSArMzA1LDEwIEBAIGludCBkcHVfY29yZV9wZXJmX2NydGNfdXBkYXRlKHN0cnVjdCBkcm1fY3J0 YyAqY3J0YywKIAkJaW50IHBhcmFtc19jaGFuZ2VkLCBib29sIHN0b3BfcmVxKQogewogCXN0cnVj dCBkcHVfY29yZV9wZXJmX3BhcmFtcyAqbmV3LCAqb2xkOwotCWludCB1cGRhdGVfYnVzID0gMCwg dXBkYXRlX2NsayA9IDA7CisJYm9vbCB1cGRhdGVfYnVzID0gZmFsc2UsIHVwZGF0ZV9jbGsgPSBm YWxzZTsKIAl1NjQgY2xrX3JhdGUgPSAwOwogCXN0cnVjdCBkcHVfY3J0YyAqZHB1X2NydGM7CiAJ c3RydWN0IGRwdV9jcnRjX3N0YXRlICpkcHVfY3N0YXRlOwotCWludCBpOwogCXN0cnVjdCBtc21f ZHJtX3ByaXZhdGUgKnByaXY7CiAJc3RydWN0IGRwdV9rbXMgKmttczsKIAlpbnQgcmV0OwpAQCAt MzYwLDYyICszMzUsNDkgQEAgaW50IGRwdV9jb3JlX3BlcmZfY3J0Y191cGRhdGUoc3RydWN0IGRy bV9jcnRjICpjcnRjLAogCW5ldyA9ICZkcHVfY3N0YXRlLT5uZXdfcGVyZjsKIAogCWlmIChjcnRj LT5lbmFibGVkICYmICFzdG9wX3JlcSkgewotCQlmb3IgKGkgPSAwOyBpIDwgRFBVX0NPUkVfUEVS Rl9EQVRBX0JVU19JRF9NQVg7IGkrKykgewotCQkJLyoKLQkJCSAqIGNhc2VzIGZvciBidXMgYmFu ZHdpZHRoIHVwZGF0ZS4KLQkJCSAqIDEuIG5ldyBiYW5kd2lkdGggdm90ZSAtICJhYiBvciBpYiB2 b3RlIiBpcyBoaWdoZXIKLQkJCSAqICAgIHRoYW4gY3VycmVudCB2b3RlIGZvciB1cGRhdGUgcmVx dWVzdC4KLQkJCSAqIDIuIG5ldyBiYW5kd2lkdGggdm90ZSAtICJhYiBvciBpYiB2b3RlIiBpcyBs b3dlcgotCQkJICogICAgdGhhbiBjdXJyZW50IHZvdGUgYXQgZW5kIG9mIGNvbW1pdCBvciBzdG9w LgotCQkJICovCi0JCQlpZiAoKHBhcmFtc19jaGFuZ2VkICYmICgobmV3LT5id19jdGxbaV0gPgot CQkJCQkJb2xkLT5id19jdGxbaV0pIHx8Ci0JCQkJICAobmV3LT5tYXhfcGVyX3BpcGVfaWJbaV0g PgotCQkJCQkJb2xkLT5tYXhfcGVyX3BpcGVfaWJbaV0pKSkgfHwKLQkJCSAgICAoIXBhcmFtc19j aGFuZ2VkICYmICgobmV3LT5id19jdGxbaV0gPAotCQkJCQkJb2xkLT5id19jdGxbaV0pIHx8Ci0J CQkJICAobmV3LT5tYXhfcGVyX3BpcGVfaWJbaV0gPAotCQkJCQkJb2xkLT5tYXhfcGVyX3BpcGVf aWJbaV0pKSkpIHsKLQkJCQlEUFVfREVCVUcoCi0JCQkJCSJjcnRjPSVkIHA9JWQgbmV3X2J3PSVs bHUsb2xkX2J3PSVsbHVcbiIsCi0JCQkJCWNydGMtPmJhc2UuaWQsIHBhcmFtc19jaGFuZ2VkLAot CQkJCQluZXctPmJ3X2N0bFtpXSwgb2xkLT5id19jdGxbaV0pOwotCQkJCW9sZC0+YndfY3RsW2ld ID0gbmV3LT5id19jdGxbaV07Ci0JCQkJb2xkLT5tYXhfcGVyX3BpcGVfaWJbaV0gPQotCQkJCQkJ bmV3LT5tYXhfcGVyX3BpcGVfaWJbaV07Ci0JCQkJdXBkYXRlX2J1cyB8PSBCSVQoaSk7Ci0JCQl9 CisJCS8qCisJCSAqIGNhc2VzIGZvciBidXMgYmFuZHdpZHRoIHVwZGF0ZS4KKwkJICogMS4gbmV3 IGJhbmR3aWR0aCB2b3RlIC0gImFiIG9yIGliIHZvdGUiIGlzIGhpZ2hlcgorCQkgKiAgICB0aGFu IGN1cnJlbnQgdm90ZSBmb3IgdXBkYXRlIHJlcXVlc3QuCisJCSAqIDIuIG5ldyBiYW5kd2lkdGgg dm90ZSAtICJhYiBvciBpYiB2b3RlIiBpcyBsb3dlcgorCQkgKiAgICB0aGFuIGN1cnJlbnQgdm90 ZSBhdCBlbmQgb2YgY29tbWl0IG9yIHN0b3AuCisJCSAqLworCQlpZiAoKHBhcmFtc19jaGFuZ2Vk ICYmICgobmV3LT5id19jdGwgPiBvbGQtPmJ3X2N0bCkgfHwKKwkJCShuZXctPm1heF9wZXJfcGlw ZV9pYiA+IG9sZC0+bWF4X3Blcl9waXBlX2liKSkpCXx8CisJCQkoIXBhcmFtc19jaGFuZ2VkICYm ICgobmV3LT5id19jdGwgPCBvbGQtPmJ3X2N0bCkgfHwKKwkJCShuZXctPm1heF9wZXJfcGlwZV9p YiA8IG9sZC0+bWF4X3Blcl9waXBlX2liKSkpKSB7CisJCQlEUFVfREVCVUcoImNydGM9JWQgcD0l ZCBuZXdfYnc9JWxsdSxvbGRfYnc9JWxsdVxuIiwKKwkJCQljcnRjLT5iYXNlLmlkLCBwYXJhbXNf Y2hhbmdlZCwKKwkJCQluZXctPmJ3X2N0bCwgb2xkLT5id19jdGwpOworCQkJb2xkLT5id19jdGwg PSBuZXctPmJ3X2N0bDsKKwkJCW9sZC0+bWF4X3Blcl9waXBlX2liID0gbmV3LT5tYXhfcGVyX3Bp cGVfaWI7CisJCQl1cGRhdGVfYnVzID0gdHJ1ZTsKIAkJfQogCiAJCWlmICgocGFyYW1zX2NoYW5n ZWQgJiYKLQkJCQkobmV3LT5jb3JlX2Nsa19yYXRlID4gb2xkLT5jb3JlX2Nsa19yYXRlKSkgfHwK LQkJCQkoIXBhcmFtc19jaGFuZ2VkICYmCi0JCQkJKG5ldy0+Y29yZV9jbGtfcmF0ZSA8IG9sZC0+ Y29yZV9jbGtfcmF0ZSkpKSB7CisJCQkobmV3LT5jb3JlX2Nsa19yYXRlID4gb2xkLT5jb3JlX2Ns a19yYXRlKSkgfHwKKwkJCSghcGFyYW1zX2NoYW5nZWQgJiYKKwkJCShuZXctPmNvcmVfY2xrX3Jh dGUgPCBvbGQtPmNvcmVfY2xrX3JhdGUpKSkgewogCQkJb2xkLT5jb3JlX2Nsa19yYXRlID0gbmV3 LT5jb3JlX2Nsa19yYXRlOwotCQkJdXBkYXRlX2NsayA9IDE7CisJCQl1cGRhdGVfY2xrID0gdHJ1 ZTsKIAkJfQogCX0gZWxzZSB7CiAJCURQVV9ERUJVRygiY3J0Yz0lZCBkaXNhYmxlXG4iLCBjcnRj LT5iYXNlLmlkKTsKIAkJbWVtc2V0KG9sZCwgMCwgc2l6ZW9mKCpvbGQpKTsKIAkJbWVtc2V0KG5l dywgMCwgc2l6ZW9mKCpuZXcpKTsKLQkJdXBkYXRlX2J1cyA9IH4wOwotCQl1cGRhdGVfY2xrID0g MTsKKwkJdXBkYXRlX2J1cyA9IHRydWU7CisJCXVwZGF0ZV9jbGsgPSB0cnVlOwogCX0KLQl0cmFj ZV9kcHVfcGVyZl9jcnRjX3VwZGF0ZShjcnRjLT5iYXNlLmlkLAotCQkJCW5ldy0+YndfY3RsW0RQ VV9DT1JFX1BFUkZfREFUQV9CVVNfSURfTU5PQ10sCi0JCQkJbmV3LT5id19jdGxbRFBVX0NPUkVf UEVSRl9EQVRBX0JVU19JRF9MTENDXSwKLQkJCQluZXctPmJ3X2N0bFtEUFVfQ09SRV9QRVJGX0RB VEFfQlVTX0lEX0VCSV0sCi0JCQkJbmV3LT5jb3JlX2Nsa19yYXRlLCBzdG9wX3JlcSwKLQkJCQl1 cGRhdGVfYnVzLCB1cGRhdGVfY2xrKTsKLQotCWZvciAoaSA9IDA7IGkgPCBEUFVfQ09SRV9QRVJG X0RBVEFfQlVTX0lEX01BWDsgaSsrKSB7Ci0JCWlmICh1cGRhdGVfYnVzICYgQklUKGkpKSB7Ci0J CQlyZXQgPSBfZHB1X2NvcmVfcGVyZl9jcnRjX3VwZGF0ZV9idXMoa21zLCBjcnRjLCBpKTsKLQkJ CWlmIChyZXQpIHsKLQkJCQlEUFVfRVJST1IoImNydGMtJWQ6IGZhaWxlZCB0byB1cGRhdGUgYncg dm90ZSBmb3IgYnVzLSVkXG4iLAotCQkJCQkgIGNydGMtPmJhc2UuaWQsIGkpOwotCQkJCXJldHVy biByZXQ7Ci0JCQl9CisKKwl0cmFjZV9kcHVfcGVyZl9jcnRjX3VwZGF0ZShjcnRjLT5iYXNlLmlk LCBuZXctPmJ3X2N0bCwKKwkJbmV3LT5jb3JlX2Nsa19yYXRlLCBzdG9wX3JlcSwgdXBkYXRlX2J1 cywgdXBkYXRlX2Nsayk7CisKKwlpZiAodXBkYXRlX2J1cykgeworCQlyZXQgPSBfZHB1X2NvcmVf cGVyZl9jcnRjX3VwZGF0ZV9idXMoa21zLCBjcnRjKTsKKwkJaWYgKHJldCkgeworCQkJRFBVX0VS Uk9SKCJjcnRjLSVkOiBmYWlsZWQgdG8gdXBkYXRlIGJ1cyBidyB2b3RlXG4iLAorCQkJCSAgY3J0 Yy0+YmFzZS5pZCk7CisJCQlyZXR1cm4gcmV0OwogCQl9CiAJfQogCmRpZmYgLS1naXQgYS9kcml2 ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvZHB1MS9kcHVfY29yZV9wZXJmLmggYi9kcml2ZXJzL2dwdS9k cm0vbXNtL2Rpc3AvZHB1MS9kcHVfY29yZV9wZXJmLmgKaW5kZXggMzdmNTE4ODE1ZWI3Li5kMjA5 N2VmM2Q3MTYgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9j b3JlX3BlcmYuaAorKysgYi9kcml2ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvZHB1MS9kcHVfY29yZV9w ZXJmLmgKQEAgLTQyLDggKzQyLDggQEAgZW51bSBkcHVfY29yZV9wZXJmX2RhdGFfYnVzX2lkIHsK ICAqIEBjb3JlX2Nsa19yYXRlOiBjb3JlIGNsb2NrIHJhdGUgcmVxdWVzdAogICovCiBzdHJ1Y3Qg ZHB1X2NvcmVfcGVyZl9wYXJhbXMgewotCXU2NCBtYXhfcGVyX3BpcGVfaWJbRFBVX0NPUkVfUEVS Rl9EQVRBX0JVU19JRF9NQVhdOwotCXU2NCBid19jdGxbRFBVX0NPUkVfUEVSRl9EQVRBX0JVU19J RF9NQVhdOworCXU2NCBtYXhfcGVyX3BpcGVfaWI7CisJdTY0IGJ3X2N0bDsKIAl1NjQgY29yZV9j bGtfcmF0ZTsKIH07CiAKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUx L2RwdV9jcnRjLmMgYi9kcml2ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvZHB1MS9kcHVfY3J0Yy5jCmlu ZGV4IGRmZGZhNzY2ZGE4Zi4uYzRkYjYwYTg2NzJkIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9k cm0vbXNtL2Rpc3AvZHB1MS9kcHVfY3J0Yy5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlz cC9kcHUxL2RwdV9jcnRjLmMKQEAgLTEyMzUsMTkgKzEyMzUsMTQgQEAgc3RhdGljIGludCBkcHVf Y3J0Y19kZWJ1Z2ZzX3N0YXRlX3Nob3coc3RydWN0IHNlcV9maWxlICpzLCB2b2lkICp2KQogewog CXN0cnVjdCBkcm1fY3J0YyAqY3J0YyA9IChzdHJ1Y3QgZHJtX2NydGMgKikgcy0+cHJpdmF0ZTsK IAlzdHJ1Y3QgZHB1X2NydGMgKmRwdV9jcnRjID0gdG9fZHB1X2NydGMoY3J0Yyk7Ci0JaW50IGk7 CiAKIAlzZXFfcHJpbnRmKHMsICJjbGllbnQgdHlwZTogJWRcbiIsIGRwdV9jcnRjX2dldF9jbGll bnRfdHlwZShjcnRjKSk7CiAJc2VxX3ByaW50ZihzLCAiaW50Zl9tb2RlOiAlZFxuIiwgZHB1X2Ny dGNfZ2V0X2ludGZfbW9kZShjcnRjKSk7CiAJc2VxX3ByaW50ZihzLCAiY29yZV9jbGtfcmF0ZTog JWxsdVxuIiwKIAkJCWRwdV9jcnRjLT5jdXJfcGVyZi5jb3JlX2Nsa19yYXRlKTsKLQlmb3IgKGkg PSBEUFVfQ09SRV9QRVJGX0RBVEFfQlVTX0lEX01OT0M7Ci0JCQlpIDwgRFBVX0NPUkVfUEVSRl9E QVRBX0JVU19JRF9NQVg7IGkrKykgewotCQlzZXFfcHJpbnRmKHMsICJid19jdGxbJWRdOiAlbGx1 XG4iLCBpLAotCQkJCWRwdV9jcnRjLT5jdXJfcGVyZi5id19jdGxbaV0pOwotCQlzZXFfcHJpbnRm KHMsICJtYXhfcGVyX3BpcGVfaWJbJWRdOiAlbGx1XG4iLCBpLAotCQkJCWRwdV9jcnRjLT5jdXJf cGVyZi5tYXhfcGVyX3BpcGVfaWJbaV0pOwotCX0KKwlzZXFfcHJpbnRmKHMsICJid19jdGw6ICVs bHVcbiIsIGRwdV9jcnRjLT5jdXJfcGVyZi5id19jdGwpOworCXNlcV9wcmludGYocywgIm1heF9w ZXJfcGlwZV9pYjogJWxsdVxuIiwKKwkJCQlkcHVfY3J0Yy0+Y3VyX3BlcmYubWF4X3Blcl9waXBl X2liKTsKIAogCXJldHVybiAwOwogfQpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21zbS9k aXNwL2RwdTEvZHB1X3RyYWNlLmggYi9kcml2ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvZHB1MS9kcHVf dHJhY2UuaAppbmRleCA4YmI0NjA5MGJkMTYuLjFkNjhlMjE0Nzk1ZSAxMDA2NDQKLS0tIGEvZHJp dmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1X3RyYWNlLmgKKysrIGIvZHJpdmVycy9ncHUv ZHJtL21zbS9kaXNwL2RwdTEvZHB1X3RyYWNlLmgKQEAgLTE0NiwxNiArMTQ2LDEyIEBAIFRSQUNF X0VWRU5UKGRwdV90cmFjZV9jb3VudGVyLAogKQogCiBUUkFDRV9FVkVOVChkcHVfcGVyZl9jcnRj X3VwZGF0ZSwKLQlUUF9QUk9UTyh1MzIgY3J0YywgdTY0IGJ3X2N0bF9tbm9jLCB1NjQgYndfY3Rs X2xsY2MsCi0JCQl1NjQgYndfY3RsX2ViaSwgdTMyIGNvcmVfY2xrX3JhdGUsCi0JCQlib29sIHN0 b3BfcmVxLCB1MzIgdXBkYXRlX2J1cywgdTMyIHVwZGF0ZV9jbGspLAotCVRQX0FSR1MoY3J0Yywg YndfY3RsX21ub2MsIGJ3X2N0bF9sbGNjLCBid19jdGxfZWJpLCBjb3JlX2Nsa19yYXRlLAotCQlz dG9wX3JlcSwgdXBkYXRlX2J1cywgdXBkYXRlX2NsayksCisJVFBfUFJPVE8odTMyIGNydGMsIHU2 NCBid19jdGwsIHUzMiBjb3JlX2Nsa19yYXRlLAorCQkJYm9vbCBzdG9wX3JlcSwgYm9vbCB1cGRh dGVfYnVzLCBib29sIHVwZGF0ZV9jbGspLAorCVRQX0FSR1MoY3J0YywgYndfY3RsLCBjb3JlX2Ns a19yYXRlLCBzdG9wX3JlcSwgdXBkYXRlX2J1cywgdXBkYXRlX2NsayksCiAJVFBfU1RSVUNUX19l bnRyeSgKIAkJCV9fZmllbGQodTMyLCBjcnRjKQotCQkJX19maWVsZCh1NjQsIGJ3X2N0bF9tbm9j KQotCQkJX19maWVsZCh1NjQsIGJ3X2N0bF9sbGNjKQotCQkJX19maWVsZCh1NjQsIGJ3X2N0bF9l YmkpCisJCQlfX2ZpZWxkKHU2NCwgYndfY3RsKQogCQkJX19maWVsZCh1MzIsIGNvcmVfY2xrX3Jh dGUpCiAJCQlfX2ZpZWxkKGJvb2wsIHN0b3BfcmVxKQogCQkJX19maWVsZCh1MzIsIHVwZGF0ZV9i dXMpCkBAIC0xNjMsMjAgKzE1OSwxNiBAQCBUUkFDRV9FVkVOVChkcHVfcGVyZl9jcnRjX3VwZGF0 ZSwKIAkpLAogCVRQX2Zhc3RfYXNzaWduKAogCQkJX19lbnRyeS0+Y3J0YyA9IGNydGM7Ci0JCQlf X2VudHJ5LT5id19jdGxfbW5vYyA9IGJ3X2N0bF9tbm9jOwotCQkJX19lbnRyeS0+YndfY3RsX2xs Y2MgPSBid19jdGxfbGxjYzsKLQkJCV9fZW50cnktPmJ3X2N0bF9lYmkgPSBid19jdGxfZWJpOwor CQkJX19lbnRyeS0+YndfY3RsID0gYndfY3RsOwogCQkJX19lbnRyeS0+Y29yZV9jbGtfcmF0ZSA9 IGNvcmVfY2xrX3JhdGU7CiAJCQlfX2VudHJ5LT5zdG9wX3JlcSA9IHN0b3BfcmVxOwogCQkJX19l bnRyeS0+dXBkYXRlX2J1cyA9IHVwZGF0ZV9idXM7CiAJCQlfX2VudHJ5LT51cGRhdGVfY2xrID0g dXBkYXRlX2NsazsKIAkpLAogCSBUUF9wcmludGsoCi0JCSJjcnRjPSVkIGJ3X21ub2M9JWxsdSBi d19sbGNjPSVsbHUgYndfZWJpPSVsbHUgY2xrX3JhdGU9JXUgc3RvcF9yZXE9JWQgdV9idXM9JWQg dV9jbGs9JWQiLAorCQkiY3J0Yz0lZCBid19jdGw9JWxsdSBjbGtfcmF0ZT0ldSBzdG9wX3JlcT0l ZCB1X2J1cz0lZCB1X2Nsaz0lZCIsCiAJCQlfX2VudHJ5LT5jcnRjLAotCQkJX19lbnRyeS0+Yndf Y3RsX21ub2MsCi0JCQlfX2VudHJ5LT5id19jdGxfbGxjYywKLQkJCV9fZW50cnktPmJ3X2N0bF9l YmksCisJCQlfX2VudHJ5LT5id19jdGwsCiAJCQlfX2VudHJ5LT5jb3JlX2Nsa19yYXRlLAogCQkJ X19lbnRyeS0+c3RvcF9yZXEsCiAJCQlfX2VudHJ5LT51cGRhdGVfYnVzLAotLSAKMi4yMC4xCgpf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpGcmVlZHJlbm8g bWFpbGluZyBsaXN0CkZyZWVkcmVub0BsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0 cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9mcmVlZHJlbm8=