From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7120DC31E5B for ; Tue, 18 Jun 2019 20:25:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3C757206E0 for ; Tue, 18 Jun 2019 20:25:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="T+c0IJF4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730654AbfFRUZS (ORCPT ); Tue, 18 Jun 2019 16:25:18 -0400 Received: from mail-qk1-f196.google.com ([209.85.222.196]:41734 "EHLO mail-qk1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725909AbfFRUZS (ORCPT ); Tue, 18 Jun 2019 16:25:18 -0400 Received: by mail-qk1-f196.google.com with SMTP id c11so9461157qkk.8; Tue, 18 Jun 2019 13:25:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ROhAZdjghgD9JnUb16HH81QOQPe1FAQVI0H2SO92WTo=; b=T+c0IJF40dM9g5jSe1uufJlsNkIzi77noCE9YvdRgmqi9tG0FAu7HaseaKPKDBo7Px dGtG/lhDZW/RXHft/KLI/MRiv6iNGVtoC83603houA+TelUn5v9dONjbP2yog7r3RQRY UO+rtzTnVqORoFHe+/5OcZv0M27JQCsjyb9uF/c4hJ9QPeTcwOgldnePKMJp9/trrfKt mj7sw3q8ZTw3pyi335SXE5Mi2WXQKRcjbxnyxPA5aozGUMrwstTLoq5rDGQl1O25iN8O MuQYrnb54tftAJ7Vqt8FzlsrH0t5LZdFrJncc9ZGm3OdCAffyIe5uzaFUZtY9wqRc5SC lsBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ROhAZdjghgD9JnUb16HH81QOQPe1FAQVI0H2SO92WTo=; b=Cfm/QmLndFod9p94oxHPkiqcrEBx0inxLQ5BBT13qXbFAm5UorjW92jeBgZ89spfSm 9RVE5k52dHspukjNVg9X5NroNC2cFdqYH9irjgjdaQfeWt9VpKXhr1ru1xOs1e3sRUwf IjZKNrP6Fkwztt2nxjrtemUKeuAbsijeOCfkN6rx0gSQ4bKDNNjjSrOqvTvrQ0IryqJA 1MIdesfHL8Bh9kuw4fn4o1HnL0Kq38QOXzJV8iVlUFzj/zMnXOGicfRwZa592fLuYAxO Lmmrxh3z9PFk7gVOYq5xKXBpRtlYp58gvDEDG+5DzvwAPLsLYB56PEkHUiUKnfTtOgAE uiRA== X-Gm-Message-State: APjAAAU66lvrpkim4bXJu0rwOYYVvpWHKrhXBJkIBt1TiBXzqw2hI6LY vpDxEJuvOzC/3GuCQC2Fqr4= X-Google-Smtp-Source: APXvYqy+2GJNZLbc49UZDN4V+1jnd4V3xuD4H3nTEeXXD9SRUZ0uRvp/Yify3qa7ZM9dr2t9nx041g== X-Received: by 2002:a05:620a:1387:: with SMTP id k7mr41250832qki.129.1560889517194; Tue, 18 Jun 2019 13:25:17 -0700 (PDT) Received: from localhost ([2601:184:4780:7861:5010:5849:d76d:b714]) by smtp.gmail.com with ESMTPSA id a21sm9979064qkg.47.2019.06.18.13.25.16 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 18 Jun 2019 13:25:16 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, Sean Paul , Georgi Djakov , Jayant Shekhar , Sravanthi Kollukuduru , Rob Clark , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jordan Crouse , Jeykumar Sankaran , Stephen Boyd , Abhinav Kumar , freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] drm/msm/dpu: Integrate interconnect API in MDSS Date: Tue, 18 Jun 2019 13:24:10 -0700 Message-Id: <20190618202425.15259-3-robdclark@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190618202425.15259-1-robdclark@gmail.com> References: <20190618202425.15259-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jayant Shekhar The interconnect framework is designed to provide a standard kernel interface to control the settings of the interconnects on a SoC. The interconnect API uses a consumer/provider-based model, where the providers are the interconnect buses and the consumers could be various drivers. MDSS is one of the interconnect consumers which uses the interconnect APIs to get the path between endpoints and set its bandwidth requirement for the given interconnected path. Changes in v2: - Remove error log and unnecessary check (Jordan Crouse) Changes in v3: - Code clean involving variable name change, removal of extra paranthesis and variables (Matthias Kaehlcke) Changes in v4: - Add comments, spacings, tabs, proper port name and icc macro (Georgi Djakov) Changes in v5: - Commit text and parenthesis alignment (Georgi Djakov) Changes in v6: - Change to new icc_set API's (Doug Anderson) Changes in v7: - Fixed a typo Changes in v8: - Handle the of_icc_get() returning NULL case. In practice icc_set_bw() will gracefully handle the case of a NULL path, but it's probably best for clarity to keep num_paths=0 in this case. Signed-off-by: Sravanthi Kollukuduru Signed-off-by: Jayant Shekhar Signed-off-by: Rob Clark Acked-by: Georgi Djakov --- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 49 ++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c index 7316b4ab1b85..b1d0437ac7b6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c @@ -4,11 +4,15 @@ */ #include "dpu_kms.h" +#include #define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base) #define HW_INTR_STATUS 0x0010 +/* Max BW defined in KBps */ +#define MAX_BW 6800000 + struct dpu_irq_controller { unsigned long enabled_mask; struct irq_domain *domain; @@ -21,8 +25,30 @@ struct dpu_mdss { u32 hwversion; struct dss_module_power mp; struct dpu_irq_controller irq_controller; + struct icc_path *path[2]; + u32 num_paths; }; +static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev, + struct dpu_mdss *dpu_mdss) +{ + struct icc_path *path0 = of_icc_get(dev->dev, "mdp0-mem"); + struct icc_path *path1 = of_icc_get(dev->dev, "mdp1-mem"); + + if (IS_ERR_OR_NULL(path0)) + return PTR_ERR_OR_ZERO(path0); + + dpu_mdss->path[0] = path0; + dpu_mdss->num_paths = 1; + + if (!IS_ERR_OR_NULL(path1)) { + dpu_mdss->path[1] = path1; + dpu_mdss->num_paths++; + } + + return 0; +} + static void dpu_mdss_irq(struct irq_desc *desc) { struct dpu_mdss *dpu_mdss = irq_desc_get_handler_data(desc); @@ -134,7 +160,11 @@ static int dpu_mdss_enable(struct msm_mdss *mdss) { struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss); struct dss_module_power *mp = &dpu_mdss->mp; - int ret; + int ret, i; + u64 avg_bw = dpu_mdss->num_paths ? MAX_BW / dpu_mdss->num_paths : 0; + + for (i = 0; i < dpu_mdss->num_paths; i++) + icc_set_bw(dpu_mdss->path[i], avg_bw, kBps_to_icc(MAX_BW)); ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); if (ret) @@ -147,12 +177,15 @@ static int dpu_mdss_disable(struct msm_mdss *mdss) { struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss); struct dss_module_power *mp = &dpu_mdss->mp; - int ret; + int ret, i; ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); if (ret) DPU_ERROR("clock disable failed, ret:%d\n", ret); + for (i = 0; i < dpu_mdss->num_paths; i++) + icc_set_bw(dpu_mdss->path[i], 0, 0); + return ret; } @@ -163,6 +196,7 @@ static void dpu_mdss_destroy(struct drm_device *dev) struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss); struct dss_module_power *mp = &dpu_mdss->mp; int irq; + int i; pm_runtime_suspend(dev->dev); pm_runtime_disable(dev->dev); @@ -172,6 +206,9 @@ static void dpu_mdss_destroy(struct drm_device *dev) msm_dss_put_clk(mp->clk_config, mp->num_clk); devm_kfree(&pdev->dev, mp->clk_config); + for (i = 0; i < dpu_mdss->num_paths; i++) + icc_put(dpu_mdss->path[i]); + if (dpu_mdss->mmio) devm_iounmap(&pdev->dev, dpu_mdss->mmio); dpu_mdss->mmio = NULL; @@ -211,6 +248,10 @@ int dpu_mdss_init(struct drm_device *dev) } dpu_mdss->mmio_len = resource_size(res); + ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss); + if (ret) + return ret; + mp = &dpu_mdss->mp; ret = msm_dss_parse_clock(pdev, mp); if (ret) { @@ -232,14 +273,14 @@ int dpu_mdss_init(struct drm_device *dev) irq_set_chained_handler_and_data(irq, dpu_mdss_irq, dpu_mdss); + priv->mdss = &dpu_mdss->base; + pm_runtime_enable(dev->dev); pm_runtime_get_sync(dev->dev); dpu_mdss->hwversion = readl_relaxed(dpu_mdss->mmio); pm_runtime_put_sync(dev->dev); - priv->mdss = &dpu_mdss->base; - return ret; irq_error: -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Clark Subject: [PATCH 2/5] drm/msm/dpu: Integrate interconnect API in MDSS Date: Tue, 18 Jun 2019 13:24:10 -0700 Message-ID: <20190618202425.15259-3-robdclark@gmail.com> References: <20190618202425.15259-1-robdclark@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20190618202425.15259-1-robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Rob Clark , freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, David Airlie , linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Jordan Crouse , Abhinav Kumar , Stephen Boyd , Jayant Shekhar , Rob Clark , Sean Paul , Daniel Vetter , Jeykumar Sankaran , Sean Paul , Georgi Djakov , Sravanthi Kollukuduru List-Id: dri-devel@lists.freedesktop.org RnJvbTogSmF5YW50IFNoZWtoYXIgPGpzaGVraGFyQGNvZGVhdXJvcmEub3JnPgoKVGhlIGludGVy Y29ubmVjdCBmcmFtZXdvcmsgaXMgZGVzaWduZWQgdG8gcHJvdmlkZSBhCnN0YW5kYXJkIGtlcm5l bCBpbnRlcmZhY2UgdG8gY29udHJvbCB0aGUgc2V0dGluZ3Mgb2YKdGhlIGludGVyY29ubmVjdHMg b24gYSBTb0MuCgpUaGUgaW50ZXJjb25uZWN0IEFQSSB1c2VzIGEgY29uc3VtZXIvcHJvdmlkZXIt YmFzZWQgbW9kZWwsCndoZXJlIHRoZSBwcm92aWRlcnMgYXJlIHRoZSBpbnRlcmNvbm5lY3QgYnVz ZXMgYW5kIHRoZQpjb25zdW1lcnMgY291bGQgYmUgdmFyaW91cyBkcml2ZXJzLgoKTURTUyBpcyBv bmUgb2YgdGhlIGludGVyY29ubmVjdCBjb25zdW1lcnMgd2hpY2ggdXNlcyB0aGUKaW50ZXJjb25u ZWN0IEFQSXMgdG8gZ2V0IHRoZSBwYXRoIGJldHdlZW4gZW5kcG9pbnRzIGFuZApzZXQgaXRzIGJh bmR3aWR0aCByZXF1aXJlbWVudCBmb3IgdGhlIGdpdmVuIGludGVyY29ubmVjdGVkCnBhdGguCgpD aGFuZ2VzIGluIHYyOgoJLSBSZW1vdmUgZXJyb3IgbG9nIGFuZCB1bm5lY2Vzc2FyeSBjaGVjayAo Sm9yZGFuIENyb3VzZSkKCkNoYW5nZXMgaW4gdjM6CgktIENvZGUgY2xlYW4gaW52b2x2aW5nIHZh cmlhYmxlIG5hbWUgY2hhbmdlLCByZW1vdmFsCgkgIG9mIGV4dHJhIHBhcmFudGhlc2lzIGFuZCB2 YXJpYWJsZXMgKE1hdHRoaWFzIEthZWhsY2tlKQoKQ2hhbmdlcyBpbiB2NDoKCS0gQWRkIGNvbW1l bnRzLCBzcGFjaW5ncywgdGFicywgcHJvcGVyIHBvcnQgbmFtZQoJICBhbmQgaWNjIG1hY3JvIChH ZW9yZ2kgRGpha292KQoKQ2hhbmdlcyBpbiB2NToKCS0gQ29tbWl0IHRleHQgYW5kIHBhcmVudGhl c2lzIGFsaWdubWVudCAoR2VvcmdpIERqYWtvdikKCkNoYW5nZXMgaW4gdjY6CgktIENoYW5nZSB0 byBuZXcgaWNjX3NldCBBUEkncyAoRG91ZyBBbmRlcnNvbikKCkNoYW5nZXMgaW4gdjc6CgktIEZp eGVkIGEgdHlwbwoKQ2hhbmdlcyBpbiB2ODoKCS0gSGFuZGxlIHRoZSBvZl9pY2NfZ2V0KCkgcmV0 dXJuaW5nIE5VTEwgY2FzZS4gIEluIHByYWN0aWNlCgkgIGljY19zZXRfYncoKSB3aWxsIGdyYWNl ZnVsbHkgaGFuZGxlIHRoZSBjYXNlIG9mIGEgTlVMTCBwYXRoLAoJICBidXQgaXQncyBwcm9iYWJs eSBiZXN0IGZvciBjbGFyaXR5IHRvIGtlZXAgbnVtX3BhdGhzPTAgaW4KCSAgdGhpcyBjYXNlLgoK U2lnbmVkLW9mZi1ieTogU3JhdmFudGhpIEtvbGx1a3VkdXJ1IDxza29sbHVrdUBjb2RlYXVyb3Jh Lm9yZz4KU2lnbmVkLW9mZi1ieTogSmF5YW50IFNoZWtoYXIgPGpzaGVraGFyQGNvZGVhdXJvcmEu b3JnPgpTaWduZWQtb2ZmLWJ5OiBSb2IgQ2xhcmsgPHJvYmRjbGFya0BjaHJvbWl1bS5vcmc+CkFj a2VkLWJ5OiBHZW9yZ2kgRGpha292IDxnZW9yZ2kuZGpha292QGxpbmFyby5vcmc+Ci0tLQogZHJp dmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1X21kc3MuYyB8IDQ5ICsrKysrKysrKysrKysr KysrKysrKystLQogMSBmaWxlIGNoYW5nZWQsIDQ1IGluc2VydGlvbnMoKyksIDQgZGVsZXRpb25z KC0pCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1X21kc3Mu YyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9tZHNzLmMKaW5kZXggNzMxNmI0 YWIxYjg1Li5iMWQwNDM3YWM3YjYgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlz cC9kcHUxL2RwdV9tZHNzLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1 X21kc3MuYwpAQCAtNCwxMSArNCwxNSBAQAogICovCiAKICNpbmNsdWRlICJkcHVfa21zLmgiCisj aW5jbHVkZSA8bGludXgvaW50ZXJjb25uZWN0Lmg+CiAKICNkZWZpbmUgdG9fZHB1X21kc3MoeCkg Y29udGFpbmVyX29mKHgsIHN0cnVjdCBkcHVfbWRzcywgYmFzZSkKIAogI2RlZmluZSBIV19JTlRS X1NUQVRVUwkJCTB4MDAxMAogCisvKiBNYXggQlcgZGVmaW5lZCBpbiBLQnBzICovCisjZGVmaW5l IE1BWF9CVwkJCQk2ODAwMDAwCisKIHN0cnVjdCBkcHVfaXJxX2NvbnRyb2xsZXIgewogCXVuc2ln bmVkIGxvbmcgZW5hYmxlZF9tYXNrOwogCXN0cnVjdCBpcnFfZG9tYWluICpkb21haW47CkBAIC0y MSw4ICsyNSwzMCBAQCBzdHJ1Y3QgZHB1X21kc3MgewogCXUzMiBod3ZlcnNpb247CiAJc3RydWN0 IGRzc19tb2R1bGVfcG93ZXIgbXA7CiAJc3RydWN0IGRwdV9pcnFfY29udHJvbGxlciBpcnFfY29u dHJvbGxlcjsKKwlzdHJ1Y3QgaWNjX3BhdGggKnBhdGhbMl07CisJdTMyIG51bV9wYXRoczsKIH07 CiAKK3N0YXRpYyBpbnQgZHB1X21kc3NfcGFyc2VfZGF0YV9idXNfaWNjX3BhdGgoc3RydWN0IGRy bV9kZXZpY2UgKmRldiwKKwkJCQkJCXN0cnVjdCBkcHVfbWRzcyAqZHB1X21kc3MpCit7CisJc3Ry dWN0IGljY19wYXRoICpwYXRoMCA9IG9mX2ljY19nZXQoZGV2LT5kZXYsICJtZHAwLW1lbSIpOwor CXN0cnVjdCBpY2NfcGF0aCAqcGF0aDEgPSBvZl9pY2NfZ2V0KGRldi0+ZGV2LCAibWRwMS1tZW0i KTsKKworCWlmIChJU19FUlJfT1JfTlVMTChwYXRoMCkpCisJCXJldHVybiBQVFJfRVJSX09SX1pF Uk8ocGF0aDApOworCisJZHB1X21kc3MtPnBhdGhbMF0gPSBwYXRoMDsKKwlkcHVfbWRzcy0+bnVt X3BhdGhzID0gMTsKKworCWlmICghSVNfRVJSX09SX05VTEwocGF0aDEpKSB7CisJCWRwdV9tZHNz LT5wYXRoWzFdID0gcGF0aDE7CisJCWRwdV9tZHNzLT5udW1fcGF0aHMrKzsKKwl9CisKKwlyZXR1 cm4gMDsKK30KKwogc3RhdGljIHZvaWQgZHB1X21kc3NfaXJxKHN0cnVjdCBpcnFfZGVzYyAqZGVz YykKIHsKIAlzdHJ1Y3QgZHB1X21kc3MgKmRwdV9tZHNzID0gaXJxX2Rlc2NfZ2V0X2hhbmRsZXJf ZGF0YShkZXNjKTsKQEAgLTEzNCw3ICsxNjAsMTEgQEAgc3RhdGljIGludCBkcHVfbWRzc19lbmFi bGUoc3RydWN0IG1zbV9tZHNzICptZHNzKQogewogCXN0cnVjdCBkcHVfbWRzcyAqZHB1X21kc3Mg PSB0b19kcHVfbWRzcyhtZHNzKTsKIAlzdHJ1Y3QgZHNzX21vZHVsZV9wb3dlciAqbXAgPSAmZHB1 X21kc3MtPm1wOwotCWludCByZXQ7CisJaW50IHJldCwgaTsKKwl1NjQgYXZnX2J3ID0gZHB1X21k c3MtPm51bV9wYXRocyA/IE1BWF9CVyAvIGRwdV9tZHNzLT5udW1fcGF0aHMgOiAwOworCisJZm9y IChpID0gMDsgaSA8IGRwdV9tZHNzLT5udW1fcGF0aHM7IGkrKykKKwkJaWNjX3NldF9idyhkcHVf bWRzcy0+cGF0aFtpXSwgYXZnX2J3LCBrQnBzX3RvX2ljYyhNQVhfQlcpKTsKIAogCXJldCA9IG1z bV9kc3NfZW5hYmxlX2NsayhtcC0+Y2xrX2NvbmZpZywgbXAtPm51bV9jbGssIHRydWUpOwogCWlm IChyZXQpCkBAIC0xNDcsMTIgKzE3NywxNSBAQCBzdGF0aWMgaW50IGRwdV9tZHNzX2Rpc2FibGUo c3RydWN0IG1zbV9tZHNzICptZHNzKQogewogCXN0cnVjdCBkcHVfbWRzcyAqZHB1X21kc3MgPSB0 b19kcHVfbWRzcyhtZHNzKTsKIAlzdHJ1Y3QgZHNzX21vZHVsZV9wb3dlciAqbXAgPSAmZHB1X21k c3MtPm1wOwotCWludCByZXQ7CisJaW50IHJldCwgaTsKIAogCXJldCA9IG1zbV9kc3NfZW5hYmxl X2NsayhtcC0+Y2xrX2NvbmZpZywgbXAtPm51bV9jbGssIGZhbHNlKTsKIAlpZiAocmV0KQogCQlE UFVfRVJST1IoImNsb2NrIGRpc2FibGUgZmFpbGVkLCByZXQ6JWRcbiIsIHJldCk7CiAKKwlmb3Ig KGkgPSAwOyBpIDwgZHB1X21kc3MtPm51bV9wYXRoczsgaSsrKQorCQlpY2Nfc2V0X2J3KGRwdV9t ZHNzLT5wYXRoW2ldLCAwLCAwKTsKKwogCXJldHVybiByZXQ7CiB9CiAKQEAgLTE2Myw2ICsxOTYs NyBAQCBzdGF0aWMgdm9pZCBkcHVfbWRzc19kZXN0cm95KHN0cnVjdCBkcm1fZGV2aWNlICpkZXYp CiAJc3RydWN0IGRwdV9tZHNzICpkcHVfbWRzcyA9IHRvX2RwdV9tZHNzKHByaXYtPm1kc3MpOwog CXN0cnVjdCBkc3NfbW9kdWxlX3Bvd2VyICptcCA9ICZkcHVfbWRzcy0+bXA7CiAJaW50IGlycTsK KwlpbnQgaTsKIAogCXBtX3J1bnRpbWVfc3VzcGVuZChkZXYtPmRldik7CiAJcG1fcnVudGltZV9k aXNhYmxlKGRldi0+ZGV2KTsKQEAgLTE3Miw2ICsyMDYsOSBAQCBzdGF0aWMgdm9pZCBkcHVfbWRz c19kZXN0cm95KHN0cnVjdCBkcm1fZGV2aWNlICpkZXYpCiAJbXNtX2Rzc19wdXRfY2xrKG1wLT5j bGtfY29uZmlnLCBtcC0+bnVtX2Nsayk7CiAJZGV2bV9rZnJlZSgmcGRldi0+ZGV2LCBtcC0+Y2xr X2NvbmZpZyk7CiAKKwlmb3IgKGkgPSAwOyBpIDwgZHB1X21kc3MtPm51bV9wYXRoczsgaSsrKQor CQlpY2NfcHV0KGRwdV9tZHNzLT5wYXRoW2ldKTsKKwogCWlmIChkcHVfbWRzcy0+bW1pbykKIAkJ ZGV2bV9pb3VubWFwKCZwZGV2LT5kZXYsIGRwdV9tZHNzLT5tbWlvKTsKIAlkcHVfbWRzcy0+bW1p byA9IE5VTEw7CkBAIC0yMTEsNiArMjQ4LDEwIEBAIGludCBkcHVfbWRzc19pbml0KHN0cnVjdCBk cm1fZGV2aWNlICpkZXYpCiAJfQogCWRwdV9tZHNzLT5tbWlvX2xlbiA9IHJlc291cmNlX3NpemUo cmVzKTsKIAorCXJldCA9IGRwdV9tZHNzX3BhcnNlX2RhdGFfYnVzX2ljY19wYXRoKGRldiwgZHB1 X21kc3MpOworCWlmIChyZXQpCisJCXJldHVybiByZXQ7CisKIAltcCA9ICZkcHVfbWRzcy0+bXA7 CiAJcmV0ID0gbXNtX2Rzc19wYXJzZV9jbG9jayhwZGV2LCBtcCk7CiAJaWYgKHJldCkgewpAQCAt MjMyLDE0ICsyNzMsMTQgQEAgaW50IGRwdV9tZHNzX2luaXQoc3RydWN0IGRybV9kZXZpY2UgKmRl dikKIAlpcnFfc2V0X2NoYWluZWRfaGFuZGxlcl9hbmRfZGF0YShpcnEsIGRwdV9tZHNzX2lycSwK IAkJCQkJIGRwdV9tZHNzKTsKIAorCXByaXYtPm1kc3MgPSAmZHB1X21kc3MtPmJhc2U7CisKIAlw bV9ydW50aW1lX2VuYWJsZShkZXYtPmRldik7CiAKIAlwbV9ydW50aW1lX2dldF9zeW5jKGRldi0+ ZGV2KTsKIAlkcHVfbWRzcy0+aHd2ZXJzaW9uID0gcmVhZGxfcmVsYXhlZChkcHVfbWRzcy0+bW1p byk7CiAJcG1fcnVudGltZV9wdXRfc3luYyhkZXYtPmRldik7CiAKLQlwcml2LT5tZHNzID0gJmRw dV9tZHNzLT5iYXNlOwotCiAJcmV0dXJuIHJldDsKIAogaXJxX2Vycm9yOgotLSAKMi4yMC4xCgpf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpGcmVlZHJlbm8g bWFpbGluZyBsaXN0CkZyZWVkcmVub0BsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0 cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9mcmVlZHJlbm8=