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From: Thierry Reding <thierry.reding@gmail.com>
To: Jon Hunter <jonathanh@nvidia.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
	stable@vger.kernel.org
Subject: Re: [PATCH 1/3] arm64: tegra: Fix AGIC register range
Date: Thu, 20 Jun 2019 11:13:07 +0200	[thread overview]
Message-ID: <20190620091307.GF26689@ulmo> (raw)
In-Reply-To: <20190620081702.17209-2-jonathanh@nvidia.com>

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On Thu, Jun 20, 2019 at 09:17:00AM +0100, Jon Hunter wrote:
> The Tegra AGIC interrupt controller is an ARM GIC400 interrupt
> controller. Per the ARM GIC device-tree binding, the first address
> region is for the GIC distributor registers and the second address
> region is for the GIC CPU interface registers. The address space for
> the distributor registers is 4kB, but currently this is incorrectly
> defined as 8kB for the Tegra AGIC and overlaps with the CPU interface
> registers. Correct the address space for the distributor to be 4kB.
> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied to for-5.3/arm64/dt, though I also added the following Fixes:
line:

Fixes: bcdbde433542 ("arm64: tegra: Add AGIC node for Tegra210")

Thanks,
Thierry

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  reply	other threads:[~2019-06-20  9:13 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-20  8:16 [PATCH 0/3] arm64: tegra: A few device-tree fixes Jon Hunter
2019-06-20  8:17 ` [PATCH 1/3] arm64: tegra: Fix AGIC register range Jon Hunter
2019-06-20  8:17   ` Jon Hunter
2019-06-20  9:13   ` Thierry Reding [this message]
2019-06-20  8:17 ` [PATCH 2/3] arm64: tegra: Update Jetson TX1 GPU regulator timings Jon Hunter
2019-06-20  8:17   ` Jon Hunter
2019-06-20  9:18   ` Thierry Reding
2019-06-20  8:17 ` [PATCH 3/3] arm64: tegra: Fix Jetson Nano GPU regulator Jon Hunter
2019-06-20  8:17   ` Jon Hunter
2019-06-20  9:19   ` Thierry Reding

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