From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ezequiel Garcia Subject: [PATCH v2 2/3] drm/rockchip: Add optional support for CRTC gamma LUT Date: Fri, 21 Jun 2019 18:13:45 -0300 Message-ID: <20190621211346.1324-3-ezequiel@collabora.com> References: <20190621211346.1324-1-ezequiel@collabora.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20190621211346.1324-1-ezequiel@collabora.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org Cc: Mark Rutland , devicetree@vger.kernel.org, Jacopo Mondi , linux-kernel@vger.kernel.org, Rob Herring , Douglas Anderson , linux-rockchip@lists.infradead.org, Boris Brezillon , Sean Paul , kernel@collabora.com, Ezequiel Garcia List-Id: linux-rockchip.vger.kernel.org QWRkIGFuIG9wdGlvbmFsIENSVEMgZ2FtbWEgTFVUIHN1cHBvcnQsIGFuZCBlbmFibGUgaXQgb24g UkszMjg4LgpUaGlzIGlzIGN1cnJlbnRseSBlbmFibGVkIHZpYSBhIHNlcGFyYXRlIGFkZHJlc3Mg cmVzb3VyY2UsCndoaWNoIG5lZWRzIHRvIGJlIHNwZWNpZmllZCBpbiB0aGUgZGV2aWNldHJlZS4K ClRoZSBhZGRyZXNzIHJlc291cmNlIGlzIHJlcXVpcmVkIGJlY2F1c2Ugb24gc29tZSBTb0NzLCBz dWNoIGFzClJLMzI4OCwgdGhlIExVVCBhZGRyZXNzIGlzIGFmdGVyIHRoZSBNTVUgYWRkcmVzcywg YW5kIHRoZSBsYXR0ZXIKaXMgc3VwcG9ydGVkIGJ5IGEgZGlmZmVyZW50IGRyaXZlci4gVGhpcyBw cmV2ZW50cyB0aGUgRFJNIGRyaXZlcgpmcm9tIHJlcXVlc3RpbmcgYW4gZW50aXJlIHJlZ2lzdGVy IHNwYWNlLgoKVGhlIGN1cnJlbnQgaW1wbGVtZW50YXRpb24gd29ya3MgZm9yIFJHQiAxMC1iaXQg dGFibGVzLCBhcyB0aGF0CmlzIHdoYXQgc2VlbXMgdG8gd29yayBvbiBSSzMyODguCgpTaWduZWQt b2ZmLWJ5OiBFemVxdWllbCBHYXJjaWEgPGV6ZXF1aWVsQGNvbGxhYm9yYS5jb20+Ci0tLQpDaGFu Z2VzIGZyb20gdjE6CiogZHJvcCBleHBsaWNpdCBsaW5lYXIgTFVUIGFmdGVyIGZpbmRpbmcgYSBw cm9wZXIKICB3YXkgdG8gZGlzYWJsZSBnYW1tYSBjb3JyZWN0aW9uLgoqIGF2b2lkIHNldHRpbmcg Z2FtbWEgaXMgdGhlIENSVEMgaXMgbm90IGFjdGl2ZS4KKiBzL2ludC91bnNpZ25lZCBpbnQgYXMg c3VnZ2VzdGVkIGJ5IEphY29wby4KKiBvbmx5IGVuYWJsZSBjb2xvciBtYW5hZ2VtZW50IGFuZCBz ZXQgZ2FtbWEgc2l6ZQogIGlmIGdhbW1hIExVVCBpcyBzdXBwb3J0ZWQsIHN1Z2dlc3RlZCBieSBE b3VnLgoqIGRyb3AgdGhlIHJlZy1uYW1lcyB1c2FnZSwgYW5kIGluc3RlYWQganVzdCB1c2UgaW5k ZXhlZCByZWcKICBzcGVjaWZpZXJzLCBzdWdnZXN0ZWQgYnkgRG91Zy4KCkNoYW5nZXMgZnJvbSBS RkM6CiogUmVxdWVzdCAoYW4gb3B0aW9uYWwpIGFkZHJlc3MgcmVzb3VyY2UgZm9yIHRoZSBMVVQu CiogRHJvcCBzdXBwb3J0IGZvciBSSzMzOTksIHdoaWNoIGRvZXNuJ3Qgc2VlbSB0byB3b3JrCiAg b3V0IG9mIHRoZSBib3ggYW5kIG5lZWRzIG1vcmUgcmVzZWFyY2guCiogU3VwcG9ydCBwYXNzLXRo cnUgc2V0dGluZyB3aGVuIEdBTU1BX0xVVCBpcyBOVUxMLgoqIEFkZCBhIGNoZWNrIGZvciB0aGUg Z2FtbWEgc2l6ZSwgYXMgc3VnZ2VzdGVkIGJ5IElsaWEuCiogTW92ZSBnYW1tYSBzZXR0aW5nIHRv IGF0b21pY19jb21taXRfdGFpbCwgYXMgcG9pbnRlZAogIG91dCBieSBKYWNvcG8vTGF1cmVudCwg aXMgdGhlIGNvcnJlY3Qgd2F5LgotLS0KIGRyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hp cF9kcm1fZmIuYyAgfCAgIDMgKwogZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX2Ry bV92b3AuYyB8IDExNCArKysrKysrKysrKysrKysrKysrKwogZHJpdmVycy9ncHUvZHJtL3JvY2tj aGlwL3JvY2tjaGlwX2RybV92b3AuaCB8ICAgNyArKwogZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlw L3JvY2tjaGlwX3ZvcF9yZWcuYyB8ICAgMiArCiA0IGZpbGVzIGNoYW5nZWQsIDEyNiBpbnNlcnRp b25zKCspCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX2Ry bV9mYi5jIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX2RybV9mYi5jCmluZGV4 IDFjNjkwNjZiNjg5NC4uYmY5YWQ2MjQwOTcxIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0v cm9ja2NoaXAvcm9ja2NoaXBfZHJtX2ZiLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlw L3JvY2tjaGlwX2RybV9mYi5jCkBAIC0xNiw2ICsxNiw3IEBACiAjaW5jbHVkZSAicm9ja2NoaXBf ZHJtX2ZiLmgiCiAjaW5jbHVkZSAicm9ja2NoaXBfZHJtX2dlbS5oIgogI2luY2x1ZGUgInJvY2tj aGlwX2RybV9wc3IuaCIKKyNpbmNsdWRlICJyb2NrY2hpcF9kcm1fdm9wLmgiCiAKIHN0YXRpYyBp bnQgcm9ja2NoaXBfZHJtX2ZiX2RpcnR5KHN0cnVjdCBkcm1fZnJhbWVidWZmZXIgKmZiLAogCQkJ CSBzdHJ1Y3QgZHJtX2ZpbGUgKmZpbGUsCkBAIC0xMjgsNiArMTI5LDggQEAgcm9ja2NoaXBfYXRv bWljX2hlbHBlcl9jb21taXRfdGFpbF9ycG0oc3RydWN0IGRybV9hdG9taWNfc3RhdGUgKm9sZF9z dGF0ZSkKIAogCWRybV9hdG9taWNfaGVscGVyX2NvbW1pdF9tb2Rlc2V0X2Rpc2FibGVzKGRldiwg b2xkX3N0YXRlKTsKIAorCXJvY2tjaGlwX2RybV92b3BfZ2FtbWFfc2V0KG9sZF9zdGF0ZSk7CisK IAlkcm1fYXRvbWljX2hlbHBlcl9jb21taXRfbW9kZXNldF9lbmFibGVzKGRldiwgb2xkX3N0YXRl KTsKIAogCWRybV9hdG9taWNfaGVscGVyX2NvbW1pdF9wbGFuZXMoZGV2LCBvbGRfc3RhdGUsCmRp ZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfZHJtX3ZvcC5jIGIv ZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX2RybV92b3AuYwppbmRleCAxMmVkNTI2 NWE5MGIuLmNmYTcwNzczYTliYyAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlw L3JvY2tjaGlwX2RybV92b3AuYworKysgYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2No aXBfZHJtX3ZvcC5jCkBAIC0xMzcsNiArMTM3LDcgQEAgc3RydWN0IHZvcCB7CiAKIAl1aW50MzJf dCAqcmVnc2JhazsKIAl2b2lkIF9faW9tZW0gKnJlZ3M7CisJdm9pZCBfX2lvbWVtICpsdXRfcmVn czsKIAogCS8qIHBoeXNpY2FsIG1hcCBsZW5ndGggb2Ygdm9wIHJlZ2lzdGVyICovCiAJdWludDMy X3QgbGVuOwpAQCAtMTE1Myw2ICsxMTU0LDEwMiBAQCBzdGF0aWMgdm9pZCB2b3Bfd2FpdF9mb3Jf aXJxX2hhbmRsZXIoc3RydWN0IHZvcCAqdm9wKQogCXN5bmNocm9uaXplX2lycSh2b3AtPmlycSk7 CiB9CiAKK3N0YXRpYyBib29sIHZvcF9kc3BfbHV0X2lzX2VuYWJsZShzdHJ1Y3Qgdm9wICp2b3Ap Cit7CisJcmV0dXJuIHZvcF9yZWFkX3JlZyh2b3AsIDAsICZ2b3AtPmRhdGEtPmNvbW1vbi0+ZHNw X2x1dF9lbik7Cit9CisKK3N0YXRpYyB2b2lkIHZvcF9jcnRjX3dyaXRlX2dhbW1hX2x1dChzdHJ1 Y3Qgdm9wICp2b3AsIHN0cnVjdCBkcm1fY3J0YyAqY3J0YykKK3sKKwlzdHJ1Y3QgZHJtX2NvbG9y X2x1dCAqbHV0ID0gY3J0Yy0+c3RhdGUtPmdhbW1hX2x1dC0+ZGF0YTsKKwl1bnNpZ25lZCBpbnQg aTsKKworCWZvciAoaSA9IDA7IGkgPCBjcnRjLT5nYW1tYV9zaXplOyBpKyspIHsKKwkJdTMyIHdv cmQ7CisKKwkJd29yZCA9IChkcm1fY29sb3JfbHV0X2V4dHJhY3QobHV0W2ldLnJlZCwgMTApIDw8 IDIwKSB8CisJCSAgICAgICAoZHJtX2NvbG9yX2x1dF9leHRyYWN0KGx1dFtpXS5ncmVlbiwgMTAp IDw8IDEwKSB8CisJCQlkcm1fY29sb3JfbHV0X2V4dHJhY3QobHV0W2ldLmJsdWUsIDEwKTsKKwkJ d3JpdGVsKHdvcmQsIHZvcC0+bHV0X3JlZ3MgKyBpICogNCk7CisJfQorfQorCitzdGF0aWMgdm9p ZCB2b3BfY3J0Y19nYW1tYV9zZXQoc3RydWN0IHZvcCAqdm9wLCBzdHJ1Y3QgZHJtX2NydGMgKmNy dGMsCisJCQkgICAgICAgc3RydWN0IGRybV9jcnRjX3N0YXRlICpvbGRfc3RhdGUpCit7CisJdW5z aWduZWQgaW50IGlkbGU7CisJaW50IHJldDsKKworCS8qCisJICogSW4gb3JkZXIgdG8gd3JpdGUg dGhlIExVVCB0byB0aGUgaW50ZXJuYWwgUkFNIG1lbW9yeSwKKwkgKiB3ZSBuZWVkIHRvIGZpcnN0 IG1ha2Ugc3VyZSB0aGUgZHNwX2x1dF9lbiBiaXQgaXMgY2xlYXJlZC4KKwkgKi8KKwlzcGluX2xv Y2soJnZvcC0+cmVnX2xvY2spOworCVZPUF9SRUdfU0VUKHZvcCwgY29tbW9uLCBkc3BfbHV0X2Vu LCAwKTsKKwl2b3BfY2ZnX2RvbmUodm9wKTsKKwlzcGluX3VubG9jaygmdm9wLT5yZWdfbG9jayk7 CisKKwkvKgorCSAqIElmIHRoZSBDUlRDIGlzIG5vdCBhY3RpdmUsIGRzcF9sdXRfZW4gd2lsbCBu b3QgZ2V0IGNsZWFyZWQuCisJICogQXBwYXJlbnRseSB3ZSBzdGlsbCBuZWVkIHRvIGRvIHRoZSBh Ym92ZSBzdGVwIHRvIGZvcgorCSAqIGdhbW1hIGNvcnJlY3Rpb24gdG8gYmUgZGlzYWJsZWQuCisJ ICovCisJaWYgKCFjcnRjLT5zdGF0ZS0+YWN0aXZlKQorCQlyZXR1cm47CisKKwlyZXQgPSByZWFk eF9wb2xsX3RpbWVvdXQodm9wX2RzcF9sdXRfaXNfZW5hYmxlLCB2b3AsCisJCQkgICBpZGxlLCAh aWRsZSwgNSwgMzAgKiAxMDAwKTsKKwlpZiAocmV0KSB7CisJCURSTV9ERVZfRVJST1Iodm9wLT5k ZXYsICJkaXNwbGF5IExVVCBSQU0gZW5hYmxlIHRpbWVvdXQhXG4iKTsKKwkJcmV0dXJuOworCX0K KworCXNwaW5fbG9jaygmdm9wLT5yZWdfbG9jayk7CisKKwlpZiAoY3J0Yy0+c3RhdGUtPmdhbW1h X2x1dCAmJgorCSAgICghb2xkX3N0YXRlLT5nYW1tYV9sdXQgfHwgKGNydGMtPnN0YXRlLT5nYW1t YV9sdXQtPmJhc2UuaWQgIT0KKwkJCQkgICAgICBvbGRfc3RhdGUtPmdhbW1hX2x1dC0+YmFzZS5p ZCkpKQorCQl2b3BfY3J0Y193cml0ZV9nYW1tYV9sdXQodm9wLCBjcnRjKTsKKworCVZPUF9SRUdf U0VUKHZvcCwgY29tbW9uLCBkc3BfbHV0X2VuLCAxKTsKKwl2b3BfY2ZnX2RvbmUodm9wKTsKKwlz cGluX3VubG9jaygmdm9wLT5yZWdfbG9jayk7Cit9CisKK3N0YXRpYyBpbnQgdm9wX2NydGNfYXRv bWljX2NoZWNrKHN0cnVjdCBkcm1fY3J0YyAqY3J0YywKKwkJCQkgICBzdHJ1Y3QgZHJtX2NydGNf c3RhdGUgKmNydGNfc3RhdGUpCit7CisJc3RydWN0IHZvcCAqdm9wID0gdG9fdm9wKGNydGMpOwor CisJaWYgKHZvcC0+bHV0X3JlZ3MgJiYgY3J0Y19zdGF0ZS0+Y29sb3JfbWdtdF9jaGFuZ2VkICYm CisJICAgIGNydGNfc3RhdGUtPmdhbW1hX2x1dCkgeworCQl1bnNpZ25lZCBpbnQgbGVuOworCisJ CWxlbiA9IGRybV9jb2xvcl9sdXRfc2l6ZShjcnRjX3N0YXRlLT5nYW1tYV9sdXQpOworCQlpZiAo bGVuICE9IGNydGMtPmdhbW1hX3NpemUpIHsKKwkJCURSTV9ERUJVR19LTVMoIkludmFsaWQgTFVU IHNpemU7IGdvdCAlZCwgZXhwZWN0ZWQgJWRcbiIsCisJCQkJICAgICAgbGVuLCBjcnRjLT5nYW1t YV9zaXplKTsKKwkJCXJldHVybiAtRUlOVkFMOworCQl9CisJfQorCisJcmV0dXJuIDA7Cit9CisK K3ZvaWQgcm9ja2NoaXBfZHJtX3ZvcF9nYW1tYV9zZXQoc3RydWN0IGRybV9hdG9taWNfc3RhdGUg KnN0YXRlKQoreworCXN0cnVjdCBkcm1fY3J0Y19zdGF0ZSAqb2xkX2NydGNfc3RhdGU7CisJc3Ry dWN0IGRybV9jcnRjICpjcnRjOworCXVuc2lnbmVkIGludCBpOworCisJZm9yX2VhY2hfb2xkX2Ny dGNfaW5fc3RhdGUoc3RhdGUsIGNydGMsIG9sZF9jcnRjX3N0YXRlLCBpKSB7CisJCXN0cnVjdCB2 b3AgKnZvcCA9IHRvX3ZvcChjcnRjKTsKKworCQlpZiAodm9wLT5sdXRfcmVncyAmJiBjcnRjLT5z dGF0ZS0+Y29sb3JfbWdtdF9jaGFuZ2VkKQorCQkJdm9wX2NydGNfZ2FtbWFfc2V0KHZvcCwgY3J0 Yywgb2xkX2NydGNfc3RhdGUpOworCX0KK30KKwogc3RhdGljIHZvaWQgdm9wX2NydGNfYXRvbWlj X2ZsdXNoKHN0cnVjdCBkcm1fY3J0YyAqY3J0YywKIAkJCQkgIHN0cnVjdCBkcm1fY3J0Y19zdGF0 ZSAqb2xkX2NydGNfc3RhdGUpCiB7CkBAIC0xMjA1LDYgKzEzMDIsNyBAQCBzdGF0aWMgdm9pZCB2 b3BfY3J0Y19hdG9taWNfZmx1c2goc3RydWN0IGRybV9jcnRjICpjcnRjLAogCiBzdGF0aWMgY29u c3Qgc3RydWN0IGRybV9jcnRjX2hlbHBlcl9mdW5jcyB2b3BfY3J0Y19oZWxwZXJfZnVuY3MgPSB7 CiAJLm1vZGVfZml4dXAgPSB2b3BfY3J0Y19tb2RlX2ZpeHVwLAorCS5hdG9taWNfY2hlY2sgPSB2 b3BfY3J0Y19hdG9taWNfY2hlY2ssCiAJLmF0b21pY19mbHVzaCA9IHZvcF9jcnRjX2F0b21pY19m bHVzaCwKIAkuYXRvbWljX2VuYWJsZSA9IHZvcF9jcnRjX2F0b21pY19lbmFibGUsCiAJLmF0b21p Y19kaXNhYmxlID0gdm9wX2NydGNfYXRvbWljX2Rpc2FibGUsCkBAIC0xMzIzLDYgKzE0MjEsNyBA QCBzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9jcnRjX2Z1bmNzIHZvcF9jcnRjX2Z1bmNzID0gewog CS5kaXNhYmxlX3ZibGFuayA9IHZvcF9jcnRjX2Rpc2FibGVfdmJsYW5rLAogCS5zZXRfY3JjX3Nv dXJjZSA9IHZvcF9jcnRjX3NldF9jcmNfc291cmNlLAogCS52ZXJpZnlfY3JjX3NvdXJjZSA9IHZv cF9jcnRjX3ZlcmlmeV9jcmNfc291cmNlLAorCS5nYW1tYV9zZXQgPSBkcm1fYXRvbWljX2hlbHBl cl9sZWdhY3lfZ2FtbWFfc2V0LAogfTsKIAogc3RhdGljIHZvaWQgdm9wX2ZiX3VucmVmX3dvcmtl cihzdHJ1Y3QgZHJtX2ZsaXBfd29yayAqd29yaywgdm9pZCAqdmFsKQpAQCAtMTQ4MCw2ICsxNTc5 LDEwIEBAIHN0YXRpYyBpbnQgdm9wX2NyZWF0ZV9jcnRjKHN0cnVjdCB2b3AgKnZvcCkKIAkJZ290 byBlcnJfY2xlYW51cF9wbGFuZXM7CiAKIAlkcm1fY3J0Y19oZWxwZXJfYWRkKGNydGMsICZ2b3Bf Y3J0Y19oZWxwZXJfZnVuY3MpOworCWlmICh2b3AtPmx1dF9yZWdzKSB7CisJCWRybV9tb2RlX2Ny dGNfc2V0X2dhbW1hX3NpemUoY3J0Yywgdm9wX2RhdGEtPmx1dF9zaXplKTsKKwkJZHJtX2NydGNf ZW5hYmxlX2NvbG9yX21nbXQoY3J0YywgMCwgZmFsc2UsIHZvcF9kYXRhLT5sdXRfc2l6ZSk7CisJ fQogCiAJLyoKIAkgKiBDcmVhdGUgZHJtX3BsYW5lcyBmb3Igb3ZlcmxheSB3aW5kb3dzIHdpdGgg cG9zc2libGVfY3J0Y3MgcmVzdHJpY3RlZApAQCAtMTc3Niw2ICsxODc5LDE3IEBAIHN0YXRpYyBp bnQgdm9wX2JpbmQoc3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgZGV2aWNlICptYXN0ZXIsIHZv aWQgKmRhdGEpCiAJaWYgKElTX0VSUih2b3AtPnJlZ3MpKQogCQlyZXR1cm4gUFRSX0VSUih2b3At PnJlZ3MpOwogCisJcmVzID0gcGxhdGZvcm1fZ2V0X3Jlc291cmNlKHBkZXYsIElPUkVTT1VSQ0Vf TUVNLCAxKTsKKwlpZiAocmVzKSB7CisJCWlmICghdm9wX2RhdGEtPmx1dF9zaXplKSB7CisJCQlE Uk1fREVWX0VSUk9SKGRldiwgIm5vIGdhbW1hIExVVCBzaXplIGRlZmluZWRcbiIpOworCQkJcmV0 dXJuIC1FSU5WQUw7CisJCX0KKwkJdm9wLT5sdXRfcmVncyA9IGRldm1faW9yZW1hcF9yZXNvdXJj ZShkZXYsIHJlcyk7CisJCWlmIChJU19FUlIodm9wLT5sdXRfcmVncykpCisJCQlyZXR1cm4gUFRS X0VSUih2b3AtPmx1dF9yZWdzKTsKKwl9CisKIAl2b3AtPnJlZ3NiYWsgPSBkZXZtX2t6YWxsb2Mo ZGV2LCB2b3AtPmxlbiwgR0ZQX0tFUk5FTCk7CiAJaWYgKCF2b3AtPnJlZ3NiYWspCiAJCXJldHVy biAtRU5PTUVNOwpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlw X2RybV92b3AuaCBiL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hpcF9kcm1fdm9wLmgK aW5kZXggMjE0OWE4ODljMjlkLi5iZDFiY2Q1YTE0ZTkgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1 L2RybS9yb2NrY2hpcC9yb2NrY2hpcF9kcm1fdm9wLmgKKysrIGIvZHJpdmVycy9ncHUvZHJtL3Jv Y2tjaGlwL3JvY2tjaGlwX2RybV92b3AuaApAQCAtNyw2ICs3LDggQEAKICNpZm5kZWYgX1JPQ0tD SElQX0RSTV9WT1BfSAogI2RlZmluZSBfUk9DS0NISVBfRFJNX1ZPUF9ICiAKKyNpbmNsdWRlIDxk cm0vZHJtX2F0b21pYy5oPgorCiAvKgogICogbWFqb3I6IElQIG1ham9yIHZlcnNpb24sIHVzZWQg Zm9yIElQIHN0cnVjdHVyZQogICogbWlub3I6IGJpZyBmZWF0dXJlIGNoYW5nZSB1bmRlciBzYW1l IHN0cnVjdHVyZQpAQCAtNjcsNiArNjksNyBAQCBzdHJ1Y3Qgdm9wX2NvbW1vbiB7CiAJc3RydWN0 IHZvcF9yZWcgZGl0aGVyX2Rvd25fbW9kZTsKIAlzdHJ1Y3Qgdm9wX3JlZyBkaXRoZXJfZG93bl9l bjsKIAlzdHJ1Y3Qgdm9wX3JlZyBkaXRoZXJfdXA7CisJc3RydWN0IHZvcF9yZWcgZHNwX2x1dF9l bjsKIAlzdHJ1Y3Qgdm9wX3JlZyBnYXRlX2VuOwogCXN0cnVjdCB2b3BfcmVnIG1tdV9lbjsKIAlz dHJ1Y3Qgdm9wX3JlZyBvdXRfbW9kZTsKQEAgLTE3MCw2ICsxNzMsNyBAQCBzdHJ1Y3Qgdm9wX2Rh dGEgewogCWNvbnN0IHN0cnVjdCB2b3Bfd2luX3l1djJ5dXZfZGF0YSAqd2luX3l1djJ5dXY7CiAJ Y29uc3Qgc3RydWN0IHZvcF93aW5fZGF0YSAqd2luOwogCXVuc2lnbmVkIGludCB3aW5fc2l6ZTsK Kwl1bnNpZ25lZCBpbnQgbHV0X3NpemU7CiAKICNkZWZpbmUgVk9QX0ZFQVRVUkVfT1VUUFVUX1JH QjEwCUJJVCgwKQogI2RlZmluZSBWT1BfRkVBVFVSRV9JTlRFUk5BTF9SR0IJQklUKDEpCkBAIC0z NzMsNCArMzc3LDcgQEAgc3RhdGljIGlubGluZSBpbnQgc2NsX3ZvcF9jYWxfbGJfbW9kZShpbnQg d2lkdGgsIGJvb2wgaXNfeXV2KQogfQogCiBleHRlcm4gY29uc3Qgc3RydWN0IGNvbXBvbmVudF9v cHMgdm9wX2NvbXBvbmVudF9vcHM7CisKK3ZvaWQgcm9ja2NoaXBfZHJtX3ZvcF9nYW1tYV9zZXQo c3RydWN0IGRybV9hdG9taWNfc3RhdGUgKnN0YXRlKTsKKwogI2VuZGlmIC8qIF9ST0NLQ0hJUF9E Uk1fVk9QX0ggKi8KZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hp cF92b3BfcmVnLmMgYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfdm9wX3JlZy5j CmluZGV4IDdiOWM3NDc1MGY2ZC4uMzBkNDllZmYzNjcwIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dw dS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfdm9wX3JlZy5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9y b2NrY2hpcC9yb2NrY2hpcF92b3BfcmVnLmMKQEAgLTU5Myw2ICs1OTMsNyBAQCBzdGF0aWMgY29u c3Qgc3RydWN0IHZvcF9jb21tb24gcmszMjg4X2NvbW1vbiA9IHsKIAkuZGl0aGVyX2Rvd25fZW4g PSBWT1BfUkVHKFJLMzI4OF9EU1BfQ1RSTDEsIDB4MSwgMiksCiAJLnByZV9kaXRoZXJfZG93biA9 IFZPUF9SRUcoUkszMjg4X0RTUF9DVFJMMSwgMHgxLCAxKSwKIAkuZGl0aGVyX3VwID0gVk9QX1JF RyhSSzMyODhfRFNQX0NUUkwxLCAweDEsIDYpLAorCS5kc3BfbHV0X2VuID0gVk9QX1JFRyhSSzMy ODhfRFNQX0NUUkwxLCAweDEsIDApLAogCS5kYXRhX2JsYW5rID0gVk9QX1JFRyhSSzMyODhfRFNQ X0NUUkwwLCAweDEsIDE5KSwKIAkuZHNwX2JsYW5rID0gVk9QX1JFRyhSSzMyODhfRFNQX0NUUkww LCAweDMsIDE4KSwKIAkub3V0X21vZGUgPSBWT1BfUkVHKFJLMzI4OF9EU1BfQ1RSTDAsIDB4Ziwg MCksCkBAIC02NDEsNiArNjQyLDcgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCB2b3BfZGF0YSByazMy ODhfdm9wID0gewogCS5vdXRwdXQgPSAmcmszMjg4X291dHB1dCwKIAkud2luID0gcmszMjg4X3Zv cF93aW5fZGF0YSwKIAkud2luX3NpemUgPSBBUlJBWV9TSVpFKHJrMzI4OF92b3Bfd2luX2RhdGEp LAorCS5sdXRfc2l6ZSA9IDEwMjQsCiB9OwogCiBzdGF0aWMgY29uc3QgaW50IHJrMzM2OF92b3Bf aW50cnNbXSA9IHsKLS0gCjIuMjAuMQoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJl ZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGlu Zm8vZHJpLWRldmVs From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48878C43613 for ; Fri, 21 Jun 2019 21:14:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1B9D7205C9 for ; Fri, 21 Jun 2019 21:14:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726326AbfFUVOM (ORCPT ); Fri, 21 Jun 2019 17:14:12 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:58664 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726237AbfFUVOK (ORCPT ); Fri, 21 Jun 2019 17:14:10 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: ezequiel) with ESMTPSA id 6B5D628639A From: Ezequiel Garcia To: dri-devel@lists.freedesktop.org Cc: linux-rockchip@lists.infradead.org, =?UTF-8?q?Heiko=20St=C3=BCbner?= , Sandy Huang , kernel@collabora.com, Sean Paul , Boris Brezillon , Douglas Anderson , Jacopo Mondi , Ilia Mirkin , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ezequiel Garcia Subject: [PATCH v2 2/3] drm/rockchip: Add optional support for CRTC gamma LUT Date: Fri, 21 Jun 2019 18:13:45 -0300 Message-Id: <20190621211346.1324-3-ezequiel@collabora.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190621211346.1324-1-ezequiel@collabora.com> References: <20190621211346.1324-1-ezequiel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add an optional CRTC gamma LUT support, and enable it on RK3288. This is currently enabled via a separate address resource, which needs to be specified in the devicetree. The address resource is required because on some SoCs, such as RK3288, the LUT address is after the MMU address, and the latter is supported by a different driver. This prevents the DRM driver from requesting an entire register space. The current implementation works for RGB 10-bit tables, as that is what seems to work on RK3288. Signed-off-by: Ezequiel Garcia --- Changes from v1: * drop explicit linear LUT after finding a proper way to disable gamma correction. * avoid setting gamma is the CRTC is not active. * s/int/unsigned int as suggested by Jacopo. * only enable color management and set gamma size if gamma LUT is supported, suggested by Doug. * drop the reg-names usage, and instead just use indexed reg specifiers, suggested by Doug. Changes from RFC: * Request (an optional) address resource for the LUT. * Drop support for RK3399, which doesn't seem to work out of the box and needs more research. * Support pass-thru setting when GAMMA_LUT is NULL. * Add a check for the gamma size, as suggested by Ilia. * Move gamma setting to atomic_commit_tail, as pointed out by Jacopo/Laurent, is the correct way. --- drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 3 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 114 ++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 7 ++ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 + 4 files changed, 126 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c index 1c69066b6894..bf9ad6240971 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c @@ -16,6 +16,7 @@ #include "rockchip_drm_fb.h" #include "rockchip_drm_gem.h" #include "rockchip_drm_psr.h" +#include "rockchip_drm_vop.h" static int rockchip_drm_fb_dirty(struct drm_framebuffer *fb, struct drm_file *file, @@ -128,6 +129,8 @@ rockchip_atomic_helper_commit_tail_rpm(struct drm_atomic_state *old_state) drm_atomic_helper_commit_modeset_disables(dev, old_state); + rockchip_drm_vop_gamma_set(old_state); + drm_atomic_helper_commit_modeset_enables(dev, old_state); drm_atomic_helper_commit_planes(dev, old_state, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 12ed5265a90b..cfa70773a9bc 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -137,6 +137,7 @@ struct vop { uint32_t *regsbak; void __iomem *regs; + void __iomem *lut_regs; /* physical map length of vop register */ uint32_t len; @@ -1153,6 +1154,102 @@ static void vop_wait_for_irq_handler(struct vop *vop) synchronize_irq(vop->irq); } +static bool vop_dsp_lut_is_enable(struct vop *vop) +{ + return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); +} + +static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) +{ + struct drm_color_lut *lut = crtc->state->gamma_lut->data; + unsigned int i; + + for (i = 0; i < crtc->gamma_size; i++) { + u32 word; + + word = (drm_color_lut_extract(lut[i].red, 10) << 20) | + (drm_color_lut_extract(lut[i].green, 10) << 10) | + drm_color_lut_extract(lut[i].blue, 10); + writel(word, vop->lut_regs + i * 4); + } +} + +static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, + struct drm_crtc_state *old_state) +{ + unsigned int idle; + int ret; + + /* + * In order to write the LUT to the internal RAM memory, + * we need to first make sure the dsp_lut_en bit is cleared. + */ + spin_lock(&vop->reg_lock); + VOP_REG_SET(vop, common, dsp_lut_en, 0); + vop_cfg_done(vop); + spin_unlock(&vop->reg_lock); + + /* + * If the CRTC is not active, dsp_lut_en will not get cleared. + * Apparently we still need to do the above step to for + * gamma correction to be disabled. + */ + if (!crtc->state->active) + return; + + ret = readx_poll_timeout(vop_dsp_lut_is_enable, vop, + idle, !idle, 5, 30 * 1000); + if (ret) { + DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); + return; + } + + spin_lock(&vop->reg_lock); + + if (crtc->state->gamma_lut && + (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id != + old_state->gamma_lut->base.id))) + vop_crtc_write_gamma_lut(vop, crtc); + + VOP_REG_SET(vop, common, dsp_lut_en, 1); + vop_cfg_done(vop); + spin_unlock(&vop->reg_lock); +} + +static int vop_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state) +{ + struct vop *vop = to_vop(crtc); + + if (vop->lut_regs && crtc_state->color_mgmt_changed && + crtc_state->gamma_lut) { + unsigned int len; + + len = drm_color_lut_size(crtc_state->gamma_lut); + if (len != crtc->gamma_size) { + DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", + len, crtc->gamma_size); + return -EINVAL; + } + } + + return 0; +} + +void rockchip_drm_vop_gamma_set(struct drm_atomic_state *state) +{ + struct drm_crtc_state *old_crtc_state; + struct drm_crtc *crtc; + unsigned int i; + + for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) { + struct vop *vop = to_vop(crtc); + + if (vop->lut_regs && crtc->state->color_mgmt_changed) + vop_crtc_gamma_set(vop, crtc, old_crtc_state); + } +} + static void vop_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { @@ -1205,6 +1302,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { .mode_fixup = vop_crtc_mode_fixup, + .atomic_check = vop_crtc_atomic_check, .atomic_flush = vop_crtc_atomic_flush, .atomic_enable = vop_crtc_atomic_enable, .atomic_disable = vop_crtc_atomic_disable, @@ -1323,6 +1421,7 @@ static const struct drm_crtc_funcs vop_crtc_funcs = { .disable_vblank = vop_crtc_disable_vblank, .set_crc_source = vop_crtc_set_crc_source, .verify_crc_source = vop_crtc_verify_crc_source, + .gamma_set = drm_atomic_helper_legacy_gamma_set, }; static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) @@ -1480,6 +1579,10 @@ static int vop_create_crtc(struct vop *vop) goto err_cleanup_planes; drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); + if (vop->lut_regs) { + drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); + drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); + } /* * Create drm_planes for overlay windows with possible_crtcs restricted @@ -1776,6 +1879,17 @@ static int vop_bind(struct device *dev, struct device *master, void *data) if (IS_ERR(vop->regs)) return PTR_ERR(vop->regs); + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) { + if (!vop_data->lut_size) { + DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); + return -EINVAL; + } + vop->lut_regs = devm_ioremap_resource(dev, res); + if (IS_ERR(vop->lut_regs)) + return PTR_ERR(vop->lut_regs); + } + vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); if (!vop->regsbak) return -ENOMEM; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 2149a889c29d..bd1bcd5a14e9 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -7,6 +7,8 @@ #ifndef _ROCKCHIP_DRM_VOP_H #define _ROCKCHIP_DRM_VOP_H +#include + /* * major: IP major version, used for IP structure * minor: big feature change under same structure @@ -67,6 +69,7 @@ struct vop_common { struct vop_reg dither_down_mode; struct vop_reg dither_down_en; struct vop_reg dither_up; + struct vop_reg dsp_lut_en; struct vop_reg gate_en; struct vop_reg mmu_en; struct vop_reg out_mode; @@ -170,6 +173,7 @@ struct vop_data { const struct vop_win_yuv2yuv_data *win_yuv2yuv; const struct vop_win_data *win; unsigned int win_size; + unsigned int lut_size; #define VOP_FEATURE_OUTPUT_RGB10 BIT(0) #define VOP_FEATURE_INTERNAL_RGB BIT(1) @@ -373,4 +377,7 @@ static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) } extern const struct component_ops vop_component_ops; + +void rockchip_drm_vop_gamma_set(struct drm_atomic_state *state); + #endif /* _ROCKCHIP_DRM_VOP_H */ diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 7b9c74750f6d..30d49eff3670 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -593,6 +593,7 @@ static const struct vop_common rk3288_common = { .dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2), .pre_dither_down = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1), .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), + .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19), .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), @@ -641,6 +642,7 @@ static const struct vop_data rk3288_vop = { .output = &rk3288_output, .win = rk3288_vop_win_data, .win_size = ARRAY_SIZE(rk3288_vop_win_data), + .lut_size = 1024, }; static const int rk3368_vop_intrs[] = { -- 2.20.1