From: Eduardo Habkost <ehabkost@redhat.com>
To: qemu-devel@nongnu.org
Cc: Igor Mammedov <imammedo@redhat.com>,
Jiri Denemark <jdenemar@redhat.com>,
"Daniel P. Berrange" <berrange@redhat.com>,
"Dr. David Alan Gilbert" <dgilbert@redhat.com>
Subject: [Qemu-devel] [PATCH v2 5/9] i386: Define -IBRS, -noTSX, -IBRS versions of CPU models
Date: Thu, 27 Jun 2019 21:28:40 -0300 [thread overview]
Message-ID: <20190628002844.24894-6-ehabkost@redhat.com> (raw)
In-Reply-To: <20190628002844.24894-1-ehabkost@redhat.com>
Add versions of CPU models that are equivalent to their -IBRS,
-noTSX and -IBRS variants.
The separate variants will eventually be removed and become
aliases for these CPU versions.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
(New patch, added to series in v2)
---
target/i386/cpu.c | 186 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 186 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b304c87b0f..5d33e75890 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1851,6 +1851,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Nehalem-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Nehalem-IBRS",
@@ -1907,6 +1921,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Westmere-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Westmere E56xx/L56xx/X56xx (IBRS update)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Westmere-IBRS",
@@ -1971,6 +1999,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E312xx (Sandy Bridge)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to SandyBridge-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "SandyBridge-IBRS",
@@ -2043,6 +2085,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to IvyBridge-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "IvyBridge-IBRS",
@@ -2205,6 +2261,52 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Haswell-noTSX */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { "stepping", "1" },
+ { "model-id", "Intel Core Processor (Haswell, no TSX)", },
+ { /* end of list */ }
+ },
+ },
+ {
+ .version = 3,
+ /* Equivalent to Haswell-IBRS */
+ .props = (PropValue[]) {
+ /* Restore TSX features removed by -v2 above */
+ { "hle", "on" },
+ { "rtm", "on" },
+ /*
+ * Haswell and Haswell-IBRS had stepping=4 in
+ * QEMU 4.0 and older
+ */
+ { "stepping", "4" },
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core Processor (Haswell, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ {
+ .version = 4,
+ /* Equivalent to Haswell-noTSX-IBRS */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ /* spec-ctrl was already enabled by -v3 above */
+ { "stepping", "1" },
+ { "model-id",
+ "Intel Core Processor (Haswell, no TSX, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Haswell-IBRS",
@@ -2375,6 +2477,45 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Broadwell-noTSX */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
+ { /* end of list */ }
+ },
+ },
+ {
+ .version = 3,
+ /* Equivalent to Broadwell-IBRS */
+ .props = (PropValue[]) {
+ /* Restore TSX features removed by -v2 above */
+ { "hle", "on" },
+ { "rtm", "on" },
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core Processor (Broadwell, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ {
+ .version = 4,
+ /* Equivalent to Broadwell-noTSX-IBRS */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ /* spec-ctrl was already enabled by -v3 above */
+ { "model-id",
+ "Intel Core Processor (Broadwell, no TSX, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Broadwell-IBRS",
@@ -2465,6 +2606,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Skylake)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Skylake-Client-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core Processor (Skylake, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Skylake-Client-IBRS",
@@ -2567,6 +2722,23 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Skylake-Server-IBRS */
+ .props = (PropValue[]) {
+ /* clflushopt was not added to Skylake-Server-IBRS */
+ /* TODO: add -v3 including clflushopt */
+ { "clflushopt", "off" },
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Xeon Processor (Skylake, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Skylake-Server-IBRS",
@@ -3011,6 +3183,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8000001E,
.model_id = "AMD EPYC Processor",
.cache_info = &epyc_cache_info,
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to EPYC-IBPB */
+ .props = (PropValue[]) {
+ { "ibpb", "on" },
+ { "model-id",
+ "AMD EPYC Processor (with IBPB)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "EPYC-IBPB",
--
2.18.0.rc1.1.g3f1ff2140
next prev parent reply other threads:[~2019-06-28 0:34 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-28 0:28 [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning Eduardo Habkost
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 1/9] qmp: Add "alias-of" field to query-cpu-definitions Eduardo Habkost
2019-07-02 9:26 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 2/9] i386: Add x-force-features option for testing Eduardo Habkost
2019-07-02 9:30 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 3/9] i386: Get model-id from CPU object on "-cpu help" Eduardo Habkost
2019-07-02 9:32 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 4/9] i386: Register versioned CPU models Eduardo Habkost
2019-07-02 9:38 ` Daniel P. Berrangé
2019-06-28 0:28 ` Eduardo Habkost [this message]
2019-07-02 9:40 ` [Qemu-devel] [PATCH v2 5/9] i386: Define -IBRS, -noTSX, -IBRS versions of " Daniel P. Berrangé
2019-07-02 9:50 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 6/9] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases Eduardo Habkost
2019-07-02 9:41 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 7/9] i386: Make unversioned CPU models be aliases Eduardo Habkost
2019-07-02 9:45 ` Daniel P. Berrangé
2019-07-02 13:57 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 8/9] docs: Deprecate CPU model runnability guarantees Eduardo Habkost
2019-07-02 9:46 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model Eduardo Habkost
2019-07-01 7:23 ` Xiaoyao Li
2019-07-01 20:38 ` Eduardo Habkost
2019-07-02 9:47 ` Daniel P. Berrangé
2019-07-02 13:55 ` Eduardo Habkost
2019-06-28 1:16 ` [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning no-reply
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