Re: [PATCH 11/28] drm/i915/tgl: Add power well to support 4th pipe

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, Jun 25, 2019 at 10:54:20AM -0700, Lucas De Marchi wrote:
> From: Mika Kahola <mika.kahola@intel.com>
> 
> Add power well 5 to support 4th pipe and transcoder on TGL.
> 
> Cc: James Ausmus <james.ausmus@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 33 ++++++++++++++++---
>  .../drm/i915/display/intel_display_power.h    |  3 ++
>  drivers/gpu/drm/i915/i915_reg.h               |  3 +-
>  3 files changed, 33 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 20b2009cecc6..0c7d4a363deb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -36,18 +36,24 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
>  		return "PIPE_B";
>  	case POWER_DOMAIN_PIPE_C:
>  		return "PIPE_C";
> +	case POWER_DOMAIN_PIPE_D:
> +		return "PIPE_D";
>  	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
>  		return "PIPE_A_PANEL_FITTER";
>  	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
>  		return "PIPE_B_PANEL_FITTER";
>  	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
>  		return "PIPE_C_PANEL_FITTER";
> +	case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
> +		return "PIPE_D_PANEL_FITTER";
>  	case POWER_DOMAIN_TRANSCODER_A:
>  		return "TRANSCODER_A";
>  	case POWER_DOMAIN_TRANSCODER_B:
>  		return "TRANSCODER_B";
>  	case POWER_DOMAIN_TRANSCODER_C:
>  		return "TRANSCODER_C";
> +	case POWER_DOMAIN_TRANSCODER_D:
> +		return "TRANSCODER_D";
>  	case POWER_DOMAIN_TRANSCODER_EDP:
>  		return "TRANSCODER_EDP";
>  	case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> @@ -2357,11 +2363,17 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>   *   GEN 12: DDI_A-C
>   * - FBC
>   */
> -/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
> +#define TGL_PW_5_POWER_DOMAINS (			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
> +	BIT_ULL(POWER_DOMAIN_INIT))
>  #define ICL_PW_4_POWER_DOMAINS (			\
>  	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
>  	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
>  	BIT_ULL(POWER_DOMAIN_INIT))
> +#define TGL_PW_4_POWER_DOMAINS (			\
> +	TGL_PW_5_POWER_DOMAINS |			\
> +	ICL_PW_4_POWER_DOMAINS)

I don't like mixing icl and tgl power wells like this. Makes it super
hard to figure out what goes where. So IMO do a clean split for these.

>  	/* VDSC/joining */
>  #define ICL_PW_3_POWER_DOMAINS (			\
>  	ICL_PW_4_POWER_DOMAINS |			\
> @@ -2393,11 +2405,11 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>  	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
>  	BIT_ULL(POWER_DOMAIN_INIT))
>  #define TGL_PW_3_POWER_DOMAINS (			\
> -	ICL_PW_4_POWER_DOMAINS |			\
> +	TGL_PW_4_POWER_DOMAINS |			\
>  	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
>  	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
>  	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> -	/* TODO: TRANSCODER_D */			\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
>  	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
>  	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |	\
>  	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |		\
> @@ -3779,7 +3791,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>  	},
>  	{
>  		.name = "power well 4",
> -		.domains = ICL_PW_4_POWER_DOMAINS,
> +		.domains = TGL_PW_4_POWER_DOMAINS,
>  		.ops = &hsw_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
> @@ -3789,7 +3801,18 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>  			.hsw.irq_pipe_mask = BIT(PIPE_C),
>  		}
>  	},
> -	/* TODO: power well 5 for pipe D */
> +	{
> +		.name = "power well 5",
> +		.domains = TGL_PW_5_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
> +			.hsw.has_fuses = true,
> +			.hsw.irq_pipe_mask = BIT(PIPE_D),
> +		},
> +	},
>  };
>  
>  static int
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 8f81b769bc2e..79262a5bceb4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -18,12 +18,15 @@ enum intel_display_power_domain {
>  	POWER_DOMAIN_PIPE_A,
>  	POWER_DOMAIN_PIPE_B,
>  	POWER_DOMAIN_PIPE_C,
> +	POWER_DOMAIN_PIPE_D,
>  	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
>  	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
>  	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
> +	POWER_DOMAIN_PIPE_D_PANEL_FITTER,
>  	POWER_DOMAIN_TRANSCODER_A,
>  	POWER_DOMAIN_TRANSCODER_B,
>  	POWER_DOMAIN_TRANSCODER_C,
> +	POWER_DOMAIN_TRANSCODER_D,
>  	POWER_DOMAIN_TRANSCODER_EDP,
>  	POWER_DOMAIN_TRANSCODER_EDP_VDSC,
>  	POWER_DOMAIN_TRANSCODER_DSI_A,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a2010b30ca89..687b065216eb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9132,7 +9132,8 @@ enum {
>  #define   GLK_PW_CTL_IDX_DDI_A			1
>  #define   SKL_PW_CTL_IDX_MISC_IO		0
>  
> -/* ICL - power wells */
> +/* ICL/TGL - power wells */
> +#define   TGL_PW_CTL_IDX_PW_5			4
>  #define   ICL_PW_CTL_IDX_PW_4			3
>  #define   ICL_PW_CTL_IDX_PW_3			2
>  #define   ICL_PW_CTL_IDX_PW_2			1
> -- 
> 2.21.0
> 
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-- 
Ville Syrjälä
Intel
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