From: Andrew Lunn <andrew@lunn.ch>
To: "Voon, Weifeng" <weifeng.voon@intel.com>
Cc: "David S. Miller" <davem@davemloft.net>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Jose Abreu <joabreu@synopsys.com>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
biao huang <biao.huang@mediatek.com>,
"Ong, Boon Leong" <boon.leong.ong@intel.com>,
"Kweh, Hock Leong" <hock.leong.kweh@intel.com>
Subject: Re: [PATCH v1 net-next] net: stmmac: enable clause 45 mdio support
Date: Thu, 4 Jul 2019 15:54:20 +0200 [thread overview]
Message-ID: <20190704135420.GD13859@lunn.ch> (raw)
In-Reply-To: <D6759987A7968C4889FDA6FA91D5CBC81473862D@PGSMSX103.gar.corp.intel.com>
On Thu, Jul 04, 2019 at 06:05:23AM +0000, Voon, Weifeng wrote:
> > > > > @@ -155,22 +171,26 @@ static int stmmac_mdio_read(struct mii_bus
> > > > > *bus,
> > > > int phyaddr, int phyreg)
> > > > > struct stmmac_priv *priv = netdev_priv(ndev);
> > > > > unsigned int mii_address = priv->hw->mii.addr;
> > > > > unsigned int mii_data = priv->hw->mii.data;
> > > > > - u32 v;
> > > > > - int data;
> > > > > u32 value = MII_BUSY;
> > > > > + int data = 0;
> > > > > + u32 v;
> > > > >
> > > > > value |= (phyaddr << priv->hw->mii.addr_shift)
> > > > > & priv->hw->mii.addr_mask;
> > > > > value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw-
> > > > >mii.reg_mask;
> > > > > value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
> > > > > & priv->hw->mii.clk_csr_mask;
> > > > > - if (priv->plat->has_gmac4)
> > > > > + if (priv->plat->has_gmac4) {
> > > > > value |= MII_GMAC4_READ;
> > > > > + if (phyreg & MII_ADDR_C45)
> > > > > + stmmac_mdio_c45_setup(priv, phyreg, &value, &data);
> > > > > + }
> > > > >
> > > > > if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v &
> > > > MII_BUSY),
> > > > > 100, 10000))
> > > > > return -EBUSY;
> > > > >
> > > > > + writel(data, priv->ioaddr + mii_data);
> > > >
> > > > That looks odd. Could you explain why it is needed.
> > > >
> > > > Thanks
> > > > Andrew
> > >
> > > Hi Andrew,
> > > This mdio c45 support needed to access DWC xPCS which is a Clause-45
> >
> > I mean it looks odd doing a write to the data register in the middle of
> > stmmac_mdio_read().
>
> MAC is using an indirect access to access mdio devices. In order to read,
> the driver needs to write into both mii_data and mii_address to select
> c45, read/write command, phy address, address to read, and etc.
Yes, that is all clear. The stmmac_mdio_c45_setup() does part of this
setup. There is also a write to mii_address which i snipped out when
replying. But why do you need to write to the data registers during a
read? C22 does not need this write. Are there some bits in the top of
the data register which are relevant to C45?
Thanks
Andrew
next prev parent reply other threads:[~2019-07-04 13:54 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-03 9:50 [PATCH v1 net-next] net: stmmac: enable clause 45 mdio support Voon Weifeng
2019-07-03 14:05 ` Andrew Lunn
2019-07-04 1:33 ` Voon, Weifeng
2019-07-04 3:30 ` Andrew Lunn
2019-07-04 6:05 ` Voon, Weifeng
2019-07-04 13:54 ` Andrew Lunn [this message]
2019-07-04 15:27 ` Jose Abreu
2019-07-04 15:29 ` Voon, Weifeng
2019-07-04 15:52 ` Andrew Lunn
2019-07-05 3:02 ` Voon, Weifeng
2019-07-05 4:52 ` Andrew Lunn
2019-07-05 6:43 ` Voon, Weifeng
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